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u-boot-brain/arch/riscv/cpu/ax25
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Rick Chen 8ba595b6bd riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL 
The mcache_ctl csr only can be manipulated in M mode.
Add SPL_RISCV_MMODE for U-Boot SPL to control cache
operation.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
2019-12-10 08:23:10 +08:00
..
cache.c riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL 2019-12-10 08:23:10 +08:00
cpu.c common: Move ARM cache operations out of common.h 2019-12-02 18:24:58 -05:00
Kconfig riscv: ax25: add SPL support 2019-12-10 08:23:10 +08:00
Makefile riscv: cache: Implement i/dcache [status, enable, disable] 2018-11-26 13:58:01 +08:00