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![Stefan Roese](/assets/img/avatar_default.png)
This patch now uses the correct ECC byte order (Smart Media - SMC) to be used on the 4xx NAND FLASH driver. Without this patch we have incompatible ECC byte ordering to the Linux kernel NDFC driver. Please note that we also have to enable CONFIG_MTD_NAND_ECC_SMC in drivers/mtd/nand/nand_ecc.c for correct operation. This is done with a seperate patch. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
224 lines
5.6 KiB
C
224 lines
5.6 KiB
C
/*
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* Overview:
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* Platform independend driver for NDFC (NanD Flash Controller)
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* integrated into IBM/AMCC PPC4xx cores
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*
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* (C) Copyright 2006-2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* Based on original work by
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* Thomas Gleixner
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* Copyright 2006 IBM
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if defined(CONFIG_CMD_NAND) && !defined(CONFIG_NAND_LEGACY) && \
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defined(CONFIG_NAND_NDFC)
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#include <nand.h>
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#include <linux/mtd/ndfc.h>
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#include <linux/mtd/nand_ecc.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <ppc4xx.h>
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/*
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* We need to store the info, which chip-select (CS) is used for the
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* chip number. For example on Sequoia NAND chip #0 uses
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* CS #3.
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*/
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static int ndfc_cs[NDFC_MAX_BANKS];
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static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF);
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else
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out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF);
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}
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static int ndfc_dev_ready(struct mtd_info *mtdinfo)
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{
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struct nand_chip *this = mtdinfo->priv;
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ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
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return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY);
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}
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static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
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{
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struct nand_chip *this = mtdinfo->priv;
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ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
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u32 ccr;
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ccr = in_be32((u32 *)(base + NDFC_CCR));
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ccr |= NDFC_CCR_RESET_ECC;
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out_be32((u32 *)(base + NDFC_CCR), ccr);
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}
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static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
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const u_char *dat, u_char *ecc_code)
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{
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struct nand_chip *this = mtdinfo->priv;
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ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
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u32 ecc;
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u8 *p = (u8 *)&ecc;
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ecc = in_be32((u32 *)(base + NDFC_ECC));
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/* The NDFC uses Smart Media (SMC) bytes order
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*/
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ecc_code[0] = p[2];
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ecc_code[1] = p[1];
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ecc_code[2] = p[3];
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return 0;
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}
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/*
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* Speedups for buffer read/write/verify
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*
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* NDFC allows 32bit read/write of data. So we can speed up the buffer
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* functions. No further checking, as nand_base will always read/write
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* page aligned.
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*/
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static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
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{
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struct nand_chip *this = mtdinfo->priv;
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ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
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uint32_t *p = (uint32_t *) buf;
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for (;len > 0; len -= 4)
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*p++ = in_be32((u32 *)(base + NDFC_DATA));
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}
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#ifndef CONFIG_NAND_SPL
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/*
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* Don't use these speedup functions in NAND boot image, since the image
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* has to fit into 4kByte.
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*/
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static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
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{
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struct nand_chip *this = mtdinfo->priv;
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ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
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uint32_t *p = (uint32_t *) buf;
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for (; len > 0; len -= 4)
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out_be32((u32 *)(base + NDFC_DATA), *p++);
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}
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static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
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{
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struct nand_chip *this = mtdinfo->priv;
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ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
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uint32_t *p = (uint32_t *) buf;
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for (; len > 0; len -= 4)
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if (*p++ != in_be32((u32 *)(base + NDFC_DATA)))
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return -1;
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return 0;
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}
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#endif /* #ifndef CONFIG_NAND_SPL */
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#ifndef CONFIG_SYS_NAND_BCR
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#define CONFIG_SYS_NAND_BCR 0x80002222
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#endif
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void board_nand_select_device(struct nand_chip *nand, int chip)
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{
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/*
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* Don't use "chip" to address the NAND device,
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* generate the cs from the address where it is encoded.
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*/
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ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
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int cs = ndfc_cs[chip];
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/* Set NandFlash Core Configuration Register */
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/* 1 col x 2 rows */
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out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
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out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR);
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}
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static void ndfc_select_chip(struct mtd_info *mtd, int chip)
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{
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/*
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* Nothing to do here!
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*/
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}
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int board_nand_init(struct nand_chip *nand)
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{
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int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
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ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
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static int chip = 0;
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/*
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* Save chip-select for this chip #
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*/
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ndfc_cs[chip] = cs;
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/*
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* Select required NAND chip in NDFC
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*/
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board_nand_select_device(nand, chip);
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nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA);
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nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA);
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nand->cmd_ctrl = ndfc_hwcontrol;
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nand->chip_delay = 50;
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nand->read_buf = ndfc_read_buf;
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nand->dev_ready = ndfc_dev_ready;
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nand->ecc.correct = nand_correct_data;
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nand->ecc.hwctl = ndfc_enable_hwecc;
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nand->ecc.calculate = ndfc_calculate_ecc;
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nand->ecc.mode = NAND_ECC_HW;
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nand->ecc.size = 256;
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nand->ecc.bytes = 3;
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nand->select_chip = ndfc_select_chip;
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#ifndef CONFIG_NAND_SPL
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nand->write_buf = ndfc_write_buf;
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nand->verify_buf = ndfc_verify_buf;
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#else
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/*
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* Setup EBC (CS0 only right now)
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*/
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mtebc(EBC0_CFG, 0xb8400000);
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mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR);
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mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP);
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#endif
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chip++;
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return 0;
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}
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#endif
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