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0efbbc5c61
u-boot-brain/arch/arm/mach-uniphier/arm32
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Masahiro Yamada 0efbbc5c61 ARM: uniphier: refactor L2 zero-touching code in lowlevel_init 
Here, the ldr pseudo-instruction falls into the ldr + data set.
The register access by [r1, #offset] produces shorter code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-11 17:49:13 +09:00
..
arm-mpcore.h ARM: uniphier: prepare directory structure for ARMv8 SoC support 2016-03-01 00:33:24 +09:00
cache-uniphier.c ARM: uniphier: do not compile v7_outer_cache_disable if L2 is disabled 2016-08-11 17:49:12 +09:00
cache-uniphier.h ARM: uniphier: support prefetch and touch operations for outer cache 2016-08-11 17:49:11 +09:00
debug_ll.S ARM: uniphier: rename function names ph1_* to uniphier_* 2016-04-01 00:59:47 +09:00
late_lowlevel_init.S ARM: uniphier: rename outer-cache register macros 2016-07-24 00:17:15 +09:00
lowlevel_init.S ARM: uniphier: refactor L2 zero-touching code in lowlevel_init 2016-08-11 17:49:13 +09:00
Makefile ARM: uniphier: rename outer-cache register macros 2016-07-24 00:17:15 +09:00
ssc-regs.h ARM: uniphier: rename outer-cache register macros 2016-07-24 00:17:15 +09:00
timer.c ARM: uniphier: prepare directory structure for ARMv8 SoC support 2016-03-01 00:33:24 +09:00