mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
152 lines
4.5 KiB
C
152 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015, Bachmann electronic GmbH
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/arch/mx6-ddr.h>
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/* Configure MX6Q/DUAL mmdc DDR io registers */
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static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
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/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
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.dram_sdclk_0 = 0x00000028,
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.dram_sdclk_1 = 0x00000028,
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.dram_cas = 0x00000028,
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.dram_ras = 0x00000028,
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.dram_reset = 0x00000028,
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/* SDCKE[0:1]: 100k pull-up */
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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/* SDBA2: pull-up disabled */
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.dram_sdba2 = 0x00000000,
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/* SDODT[0:1]: 100k pull-up, 48 ohm */
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.dram_sdodt0 = 0x00000028,
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.dram_sdodt1 = 0x00000028,
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/* SDQS[0:7]: Differential input, 48 ohm */
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.dram_sdqs0 = 0x00000028,
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.dram_sdqs1 = 0x00000028,
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.dram_sdqs2 = 0x00000028,
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.dram_sdqs3 = 0x00000028,
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.dram_sdqs4 = 0x00000028,
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.dram_sdqs5 = 0x00000028,
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.dram_sdqs6 = 0x00000028,
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.dram_sdqs7 = 0x00000028,
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/* DQM[0:7]: Differential input, 48 ohm */
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.dram_dqm0 = 0x00000028,
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.dram_dqm1 = 0x00000028,
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.dram_dqm2 = 0x00000028,
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.dram_dqm3 = 0x00000028,
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.dram_dqm4 = 0x00000028,
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.dram_dqm5 = 0x00000028,
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.dram_dqm6 = 0x00000028,
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.dram_dqm7 = 0x00000028,
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};
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/* Configure MX6Q/DUAL mmdc GRP io registers */
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static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = {
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/* DDR3 */
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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/* Disable DDR pullups */
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.grp_ddrpke = 0x00000000,
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/* ADDR[00:16], SDBA[0:1]: 48 ohm */
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.grp_addds = 0x00000028,
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/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */
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.grp_ctlds = 0x00000028,
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/* DATA[00:63]: Differential input, 48 ohm */
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x00000028,
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.grp_b1ds = 0x00000028,
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.grp_b2ds = 0x00000028,
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.grp_b3ds = 0x00000028,
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.grp_b4ds = 0x00000028,
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.grp_b5ds = 0x00000028,
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.grp_b6ds = 0x00000028,
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.grp_b7ds = 0x00000028,
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};
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static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = {
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/* Width of data bus: 0=16, 1=32, 2=64 */
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.dsize = 2,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32, /* 32Gb per CS */
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/* Single chip select */
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.ncs = 1,
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.cs1_mirror = 0, /* war 0 */
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.rtt_wr = 1, /* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */
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.rtt_nom = 1, /* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */ /* war 1 */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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.refsel = 1, /* Refresh cycles at 32KHz */
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.refr = 7, /* 8 refresh commands per refresh cycle */
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};
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/* MT41K128M16JT-125 */
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static struct mx6_ddr3_cfg micron_2gib_1600 = {
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.mem_speed = 1600,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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.SRT = 1,
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};
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static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = {
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/* write leveling calibration determine */
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.p0_mpwldectrl0 = 0x00260025,
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.p0_mpwldectrl1 = 0x00270021,
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.p1_mpwldectrl0 = 0x00180034,
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.p1_mpwldectrl1 = 0x00180024,
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/* Read DQS Gating calibration */
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.p0_mpdgctrl0 = 0x04380344,
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.p0_mpdgctrl1 = 0x0330032C,
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.p1_mpdgctrl0 = 0x0338033C,
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.p1_mpdgctrl1 = 0x032C0300,
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/* Read Calibration: DQS delay relative to DQ read access */
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.p0_mprddlctl = 0x3C2E3238,
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.p1_mprddlctl = 0x3A2E303C,
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/* Write Calibration: DQ/DM delay relative to DQS write access */
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.p0_mpwrdlctl = 0x36384036,
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.p1_mpwrdlctl = 0x442E4438,
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};
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static void ot1200_spl_dram_init(void)
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{
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mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs);
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mx6_dram_cfg(&ot1200_ddr_sysinfo, µn_2gib_1600_mmdc_calib,
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µn_2gib_1600);
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}
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/*
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* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
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* - we have a stack and a place to store GD, both in SRAM
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* - no variable global data is available
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*/
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void board_init_f(ulong dummy)
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{
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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/* iomux and setup of i2c */
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board_early_init_f();
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/* setup GP timer */
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timer_init();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* configure MMDC for SDRAM width/size and per-model calibration */
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ot1200_spl_dram_init();
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}
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