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https://github.com/brain-hackers/u-boot-brain
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0e890d4c2b
To further simplify config include files, unroll the km/km8309-common.h and km/km8321-common.h include files. Signed-off-by: Mario Six <mario.six@gdsys.cc>
294 lines
8.3 KiB
C
294 lines
8.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* Copyright (C) 2007 Logic Product Development, Inc.
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* Peter Barada <peterb@logicpd.com>
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* (C) Copyright 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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/* This needs to be set prior to including km83xx-common.h */
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#define CONFIG_HOSTNAME "kmvect1"
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#define CONFIG_KM_BOARD_NAME "kmvect1"
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/* at end of uboot partition, before env */
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#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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#define CONFIG_QE 1 /* Has QE */
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#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
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/* include common defines/options for all 83xx Keymile boards */
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#include "km83xx-common.h"
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/* QE microcode/firmware address */
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#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
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/* between the u-boot partition and env */
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#ifndef CONFIG_SYS_QE_FW_ADDR
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#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000
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#endif
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/*
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* System IO Config
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*/
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/* 0x14000180 SICR_1 */
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#define CONFIG_SYS_SICRL (0 \
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| SICR_1_UART1_UART1RTS \
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| SICR_1_I2C_CKSTOP \
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| SICR_1_IRQ_A_IRQ \
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| SICR_1_IRQ_B_IRQ \
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| SICR_1_GPIO_A_GPIO \
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| SICR_1_GPIO_B_GPIO \
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| SICR_1_GPIO_C_GPIO \
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| SICR_1_GPIO_D_GPIO \
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| SICR_1_GPIO_E_GPIO \
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| SICR_1_GPIO_F_GPIO \
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| SICR_1_USB_A_UART2S \
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| SICR_1_USB_B_UART2RTS \
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| SICR_1_FEC1_FEC1 \
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| SICR_1_FEC2_FEC2 \
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)
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/* 0x00080400 SICR_2 */
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#define CONFIG_SYS_SICRH (0 \
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| SICR_2_FEC3_FEC3 \
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| SICR_2_HDLC1_A_HDLC1 \
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| SICR_2_ELBC_A_LA \
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| SICR_2_ELBC_B_LCLK \
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| SICR_2_HDLC2_A_HDLC2 \
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| SICR_2_USB_D_GPIO \
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| SICR_2_PCI_PCI \
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| SICR_2_HDLC1_B_HDLC1 \
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| SICR_2_HDLC1_C_HDLC1 \
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| SICR_2_HDLC2_B_GPIO \
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| SICR_2_HDLC2_C_HDLC2 \
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| SICR_2_QUIESCE_B \
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)
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/* GPR_1 */
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#define CONFIG_SYS_GPR1 0x50008060
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#define CONFIG_SYS_GP1DIR 0x00000000
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#define CONFIG_SYS_GP1ODR 0x00000000
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#define CONFIG_SYS_GP2DIR 0xFF000000
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#define CONFIG_SYS_GP2ODR 0x00000000
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/*
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* Hardware Reset Configuration Word
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*/
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#define CONFIG_SYS_HRCW_LOW (\
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
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HRCWL_DDR_TO_SCB_CLK_2X1 | \
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HRCWL_CSB_TO_CLKIN_2X1 | \
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HRCWL_CORE_TO_CSB_2X1 | \
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HRCWL_CE_PLL_VCO_DIV_2 | \
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HRCWL_CE_TO_PLL_1X3)
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#define CONFIG_SYS_HRCW_HIGH (\
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HRCWH_PCI_AGENT | \
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HRCWH_PCI_ARBITER_DISABLE | \
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HRCWH_CORE_ENABLE | \
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HRCWH_FROM_0X00000100 | \
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HRCWH_BOOTSEQ_DISABLE | \
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HRCWH_SW_WATCHDOG_DISABLE | \
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HRCWH_ROM_LOC_LOCAL_16BIT | \
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HRCWH_BIG_ENDIAN | \
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HRCWH_LALE_NORMAL)
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#define CONFIG_SYS_DDRCDR (\
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DDRCDR_EN | \
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DDRCDR_PZ_MAXZ | \
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DDRCDR_NZ_MAXZ | \
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DDRCDR_M_ODR)
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
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#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
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SDRAM_CFG_32_BE | \
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SDRAM_CFG_SREN | \
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SDRAM_CFG_HSE)
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
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#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
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(0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
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CSCONFIG_ODT_RD_NEVER | \
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CSCONFIG_ODT_WR_ONLY_CURRENT | \
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CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_COL_BIT_10)
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#define CONFIG_SYS_DDR_MODE 0x47860242
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#define CONFIG_SYS_DDR_MODE2 0x8080c000
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#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
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(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
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(0 << TIMING_CFG0_WWT_SHIFT) | \
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(0 << TIMING_CFG0_RRT_SHIFT) | \
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(0 << TIMING_CFG0_WRT_SHIFT) | \
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(0 << TIMING_CFG0_RWT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
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(2 << TIMING_CFG1_WRTORD_SHIFT) | \
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(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
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(3 << TIMING_CFG1_WRREC_SHIFT) | \
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(7 << TIMING_CFG1_REFREC_SHIFT) | \
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(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
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(7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
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(3 << TIMING_CFG1_PRETOACT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
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(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
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(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
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(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
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(3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
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(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
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(5 << TIMING_CFG2_CPO_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
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#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LCRR_DBYP 0x80000000
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#define CONFIG_SYS_LCRR_EADC 0x00010000
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#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/*
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* MMU Setup
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*/
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#define CONFIG_SYS_IBAT7L (0)
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#define CONFIG_SYS_IBAT7U (0)
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#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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#define CONFIG_SYS_APP1_BASE 0xA0000000
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#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
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#define CONFIG_SYS_APP2_BASE 0xB0000000
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#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/*
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* Init Local Bus Memory Controller:
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*
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* Bank Bus Machine PortSz Size Device
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* ---- --- ------- ------ ----- ------
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* 2 Local UPMA 16 bit 256MB APP1
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* 3 Local GPCM 16 bit 256MB APP2
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*
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*/
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/*
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* APP1 on the local bus CS2
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*/
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#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
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#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
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#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
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BR_PS_16 | \
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BR_MS_UPMA | \
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BR_V)
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#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
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#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
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BR_PS_16 | \
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BR_V)
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#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
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OR_GPCM_CSNT | \
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OR_GPCM_ACS_DIV4 | \
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OR_GPCM_SCY_3 | \
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OR_GPCM_TRLX_SET)
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#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
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0x0000c000 | \
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MxMR_WLFx_2X)
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#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
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#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
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/*
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* MMU Setup
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*/
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/* APP1: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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/*
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* QE UEC ethernet configuration
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*/
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#define CONFIG_MV88E6352_SWITCH
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#define CONFIG_KM_MVEXTSW_ADDR 0x10
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/* ethernet port connected to simple switch 88e6122 (UEC0) */
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#define CONFIG_UEC_ETH1
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#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
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#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
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#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
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#define CONFIG_FIXED_PHY 0xFFFFFFFF
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#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */
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#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
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{devnum, speed, duplex}
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#define CONFIG_SYS_FIXED_PHY_PORTS \
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CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
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#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
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#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
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#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
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#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
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/* ethernet port connected to piggy (UEC2) */
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#define CONFIG_HAS_ETH1
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#define CONFIG_UEC_ETH2
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#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
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#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
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#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
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#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
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#define CONFIG_SYS_UEC2_PHY_ADDR 0
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#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
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#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
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#endif /* __CONFIG_H */
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