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0e68a3694d
u-boot-brain/board/freescale/ls1043ardb
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Hou Zhiqiang 0e68a3694d ARMv8/ls1043ardb: Integrate FSL PPA 
The PPA use PSCI to make secondary cores bootup. So when PPA was
enabled, add the CONFIG_ARMV8_PSCI to identify the SMP boot-method
between PSCI and spin-table.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-19 11:34:26 -07:00
..
cpld.c armv8/ls1043ardb: fix the limitation of using 'cpld reset' 2016-05-18 08:51:44 -07:00
cpld.h armv8/ls1043ardb: fix the limitation of using 'cpld reset' 2016-05-18 08:51:44 -07:00
ddr.c armv8: Move secure_ram variable out of generic global data 2016-07-15 09:01:43 -07:00
ddr.h board/freescale: Update ddr clk_adjust 2016-06-03 14:06:57 -07:00
eth.c armv8/ls1043a: Add Fman support 2015-10-29 10:34:01 -07:00
Kconfig armv8/ls1043ardb: Add LS1043ARDB board support 2015-10-29 10:34:01 -07:00
ls1043ardb_pbi.cfg armv8/ls1043ardb: Add nand boot support 2015-10-29 10:34:01 -07:00
ls1043ardb_rcw_nand.cfg armv8/ls1043ardb/rcw: change core frequency to 1600MHz 2015-12-17 08:52:18 +08:00
ls1043ardb_rcw_sd.cfg armv8/ls1043ardb/rcw: change core frequency to 1600MHz 2015-12-17 08:52:18 +08:00
ls1043ardb.c ARMv8/ls1043ardb: Integrate FSL PPA 2016-07-19 11:34:26 -07:00
MAINTAINERS armv8/ls1043ardb: add SECURE BOOT target for NOR 2015-12-15 08:57:35 +08:00
Makefile armv8/ls1043a: Add Fman support 2015-10-29 10:34:01 -07:00
README armv8: fsl-layerscape: Organize SoC overview at common location 2016-06-03 14:12:50 -07:00

README 

Overview
--------
The LS1043A Reference Design Board (RDB) is a high-performance computing,
evaluation, and development platform that supports the QorIQ LS1043A
LayerScape Architecture processor. The LS1043ARDB provides SW development
platform for the Freescale LS1043A processor series, with a complete
debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.

LS1043A SoC Overview
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
SoC overview.

 LS1043ARDB board Overview
 -----------------------
 - SERDES Connections, 4 lanes supporting:
      - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
        standard PCIe card
      - QSGMII with x4 RJ45 connector
      - XFI with x1 RJ45 connector
 - DDR Controller
     - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
 -IFC/Local Bus
    - One 128MB NOR flash 16-bit data bus
    - One 512 MB NAND flash with ECC support
    - CPLD connection
 - USB 3.0
    - Two super speed USB 3.0 Type A ports
 - SDHC: connects directly to a full SD/MMC slot
 - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
 - 4 I2C controllers
 - UART
   - Two 4-pin serial ports at up to 115.2 Kbit/s
   - Two DB9 D-Type connectors supporting one Serial port each
 - ARM JTAG support

Memory map from core's view
----------------------------
Start Address	End Address	Description		Size
0x00_0000_0000	0x00_000F_FFFF	Secure Boot ROM		1MB
0x00_0100_0000	0x00_0FFF_FFFF	CCSRBAR			240MB
0x00_1000_0000	0x00_1000_FFFF	OCRAM0			64KB
0x00_1001_0000	0x00_1001_FFFF	OCRAM1			64KB
0x00_2000_0000	0x00_20FF_FFFF	DCSR			16MB
0x00_6000_0000	0x00_67FF_FFFF	IFC - NOR Flash		128MB
0x00_7E80_0000	0x00_7E80_FFFF	IFC - NAND Flash	64KB
0x00_7FB0_0000	0x00_7FB0_0FFF	IFC - FPGA		4KB
0x00_8000_0000	0x00_FFFF_FFFF	DRAM1			2GB

Booting Options
---------------
a) NOR boot
b) NAND boot
c) SD boot