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https://github.com/brain-hackers/u-boot-brain
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4909b89ec7
LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
108 lines
3.0 KiB
C
108 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <common.h>
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#include <phy.h>
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#include <fsl-mc/ldpaa_wriop.h>
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#include <asm/io.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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u32 dpmac_to_devdisr[] = {
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[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
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[WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
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[WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
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[WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
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[WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
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[WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
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[WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
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[WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
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[WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
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[WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
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[WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
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[WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
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[WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
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[WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
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[WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
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[WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
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[WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
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[WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
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};
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static int is_device_disabled(int dpmac_id)
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{
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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u32 devdisr2 = in_le32(&gur->devdisr2);
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return dpmac_to_devdisr[dpmac_id] & devdisr2;
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}
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void wriop_dpmac_disable(int dpmac_id)
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{
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
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}
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void wriop_dpmac_enable(int dpmac_id)
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{
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
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}
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phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
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{
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enum srds_prtcl;
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if (is_device_disabled(dpmac_id + 1))
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return PHY_INTERFACE_MODE_NONE;
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if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
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return PHY_INTERFACE_MODE_SGMII;
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if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
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return PHY_INTERFACE_MODE_XGMII;
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if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
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return PHY_INTERFACE_MODE_25G_AUI;
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if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
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return PHY_INTERFACE_MODE_XLAUI;
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if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
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return PHY_INTERFACE_MODE_CAUI2;
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if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
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return PHY_INTERFACE_MODE_CAUI4;
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return PHY_INTERFACE_MODE_NONE;
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}
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#ifdef CONFIG_SYS_FSL_HAS_RGMII
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void fsl_rgmii_init(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 ec;
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#ifdef CONFIG_SYS_FSL_EC1
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ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])
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& FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK;
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ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT;
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if (!ec)
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wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID);
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#endif
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#ifdef CONFIG_SYS_FSL_EC2
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ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])
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& FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK;
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ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT;
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if (!ec)
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wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID);
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#endif
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}
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#endif
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