mirror of
https://github.com/brain-hackers/u-boot-brain
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cf04d0326b
Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
54 lines
1.2 KiB
C
54 lines
1.2 KiB
C
/*
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* board.h
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*
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* TI AM437x boards information header
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* Derived from AM335x board.
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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#include <asm/arch/omap.h>
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static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START;
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/*
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* TI AM437x EVMs define a system EEPROM that defines certain sub-fields.
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* We use these fields to in turn see what board we are on, and what
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* that might require us to set or not set.
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*/
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#define HDR_NO_OF_MAC_ADDR 3
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#define HDR_ETH_ALEN 6
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#define HDR_NAME_LEN 8
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#define DEV_ATTR_MAX_OFFSET 5
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#define DEV_ATTR_MIN_OFFSET 0
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struct am43xx_board_id {
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unsigned int magic;
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char name[HDR_NAME_LEN];
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char version[4];
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char serial[12];
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char config[32];
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char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
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};
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static inline int board_is_eposevm(void)
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{
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return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN);
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}
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static inline int board_is_gpevm(void)
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{
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return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN);
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}
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void enable_uart0_pin_mux(void);
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void enable_board_pin_mux(void);
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void enable_i2c0_pin_mux(void);
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#endif
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