mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-30 05:48:51 +09:00
![Faiz Abbas](/assets/img/avatar_default.png)
Sync with kernel dts by adding pinmuxes for mmc1 and mmc2. This fixes an issue where mmc2 (eMMC) was coming up in HS52 mode instead of the highest DDR52 mode. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
38 lines
723 B
Plaintext
38 lines
723 B
Plaintext
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
|
|
*/
|
|
|
|
|
|
/dts-v1/;
|
|
|
|
#include "dra76x.dtsi"
|
|
#include "dra7-mmc-iodelay.dtsi"
|
|
#include "dra76x-mmc-iodelay.dtsi"
|
|
#include "am572x-idk-common.dtsi"
|
|
|
|
/ {
|
|
model = "TI AM5748 IDK";
|
|
compatible = "ti,am5728-idk", "ti,dra762", "ti,dra7";
|
|
};
|
|
|
|
&qspi {
|
|
spi-max-frequency = <96000000>;
|
|
m25p80@0 {
|
|
spi-max-frequency = <96000000>;
|
|
};
|
|
};
|
|
|
|
&mmc1 {
|
|
pinctrl-names = "default", "hs";
|
|
pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
|
|
pinctrl-1 = <&mmc1_pins_hs>;
|
|
};
|
|
|
|
&mmc2 {
|
|
pinctrl-names = "default", "hs", "ddr_1_8v";
|
|
pinctrl-0 = <&mmc2_pins_default>;
|
|
pinctrl-1 = <&mmc2_pins_default>;
|
|
pinctrl-2 = <&mmc2_pins_default>;
|
|
};
|