Mingkai Hu 0d6faf2bd0 armv8/ls1043a: Implement workaround for PEX erratum A009929 ... Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>		2015-12-17 08:52:18 +08:00
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clock.h	armv8/fsl_lsch3: Change arch to fsl-layerscape	2015-10-29 10:34:00 -07:00
config.h	armv8/ls1043a: Implement workaround for PEX erratum A009929	2015-12-17 08:52:18 +08:00
cpu.h	armv8: fsl-layerscape: Make DDR non secure in MMU tables	2015-12-15 08:57:33 +08:00
fdt.h	armv8/ls1043aqds: add LS1043AQDS board support	2015-11-30 09:11:10 -08:00
fsl_serdes.h	armv8: ls2085a: Add support of LS2085A SoC	2015-11-30 09:10:47 -08:00
immap_lsch2.h	armv8/ls1043a: Implement workaround for PEX erratum A009929	2015-12-17 08:52:18 +08:00
immap_lsch3.h	armv8: Add sata support on Layerscape ARMv8 board	2015-12-15 08:57:35 +08:00
imx-regs.h	armv8/fsl_lsch3: Change arch to fsl-layerscape	2015-10-29 10:34:00 -07:00
ls2080a_stream_id.h	armv8: LS2080A: Rename LS2085A to reflect LS2080A	2015-11-30 08:53:04 -08:00
mmu.h	armv8/fsl_lsch3: Change arch to fsl-layerscape	2015-10-29 10:34:00 -07:00
mp.h	armv8/fsl_lsch3: Change arch to fsl-layerscape	2015-10-29 10:34:00 -07:00
ns_access.h	armv8/fsl_lsch2: Add fsl_lsch2 SoC	2015-10-29 10:34:00 -07:00
soc.h	armv8: Add sata support on Layerscape ARMv8 board	2015-12-15 08:57:35 +08:00
speed.h	armv8/fsl_lsch3: Change arch to fsl-layerscape	2015-10-29 10:34:00 -07:00