mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
162 lines
6.4 KiB
C
162 lines
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2000
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* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
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*/
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/* winbond access routines and defines*/
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/* from the winbond data sheet -
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The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
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Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller.
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*/
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/*ISA bridge configuration space*/
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#define W83C553F_VID 0x10AD
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#define W83C553F_DID 0x0565
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#define WINBOND_PCICONTR 0x40 /*pci control reg*/
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#define WINBOND_SGBAR 0x41 /*scatter/gather base address reg*/
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#define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/
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#define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/
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#define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/
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#define WINBOND_BTBAR 0x46 /*BIOS Timer Base Address Register*/
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#define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/
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#define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/
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#define WINBOND_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/
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#define WINBOND_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/
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#define WINBOND_CDR 0x4c /*Clock Divisor Register*/
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#define WINBOND_CSCR 0x4d /*Chip Select Control Register*/
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#define WINBOND_ATSCR 0x4e /*AT System Control register*/
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#define WINBOND_ATBCR 0x4f /*AT Bus ControL Register*/
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#define WINBOND_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/
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#define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/
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#define WINBOND_ABEER 0x62 /*Additional Break Event Enable Register*/
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#define WINBOND_DMABEER 0x63 /*DMA Break Event Enable Register*/
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#define WINDOND_IDECSR 0x40 /*IDE Control/Status Register, Function 1*/
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#define IPADCR_MBE512 0x1
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#define IPADCR_MBE640 0x2
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#define IPADCR_IPATOM4 0x10
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#define IPADCR_IPATOM5 0x20
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#define IPADCR_IPATOM6 0x40
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#define IPADCR_IPATOM7 0x80
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#define CSCR_UBIOSCSE 0x10
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#define CSCR_BIOSWP 0x20
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#define IDECSR_P0EN 0x01
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#define IDECSR_P0F16 0x02
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#define IDECSR_P1EN 0x10
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#define IDECSR_P1F16 0x20
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#define IDECSR_LEGIRQ 0x800
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/*
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* Interrupt controller
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*/
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#define W83C553F_PIC1_ICW1 CONFIG_SYS_ISA_IO + 0x20
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#define W83C553F_PIC1_ICW2 CONFIG_SYS_ISA_IO + 0x21
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#define W83C553F_PIC1_ICW3 CONFIG_SYS_ISA_IO + 0x21
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#define W83C553F_PIC1_ICW4 CONFIG_SYS_ISA_IO + 0x21
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#define W83C553F_PIC1_OCW1 CONFIG_SYS_ISA_IO + 0x21
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#define W83C553F_PIC1_OCW2 CONFIG_SYS_ISA_IO + 0x20
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#define W83C553F_PIC1_OCW3 CONFIG_SYS_ISA_IO + 0x20
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#define W83C553F_PIC1_ELC CONFIG_SYS_ISA_IO + 0x4D0
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#define W83C553F_PIC2_ICW1 CONFIG_SYS_ISA_IO + 0xA0
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#define W83C553F_PIC2_ICW2 CONFIG_SYS_ISA_IO + 0xA1
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#define W83C553F_PIC2_ICW3 CONFIG_SYS_ISA_IO + 0xA1
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#define W83C553F_PIC2_ICW4 CONFIG_SYS_ISA_IO + 0xA1
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#define W83C553F_PIC2_OCW1 CONFIG_SYS_ISA_IO + 0xA1
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#define W83C553F_PIC2_OCW2 CONFIG_SYS_ISA_IO + 0xA0
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#define W83C553F_PIC2_OCW3 CONFIG_SYS_ISA_IO + 0xA0
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#define W83C553F_PIC2_ELC CONFIG_SYS_ISA_IO + 0x4D1
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#define W83C553F_TMR1_CMOD CONFIG_SYS_ISA_IO + 0x43
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/*
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* DMA controller
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*/
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#define W83C553F_DMA1 CONFIG_SYS_ISA_IO + 0x000 /* channel 0 - 3 */
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#define W83C553F_DMA2 CONFIG_SYS_ISA_IO + 0x0C0 /* channel 4 - 7 */
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/* command/status register bit definitions */
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#define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */
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#define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */
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#define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */
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#define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */
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#define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */
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#define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */
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#define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */
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#define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */
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#define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */
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#define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */
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#define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */
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#define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */
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/* mode register bit definitions */
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#define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */
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#define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */
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#define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */
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#define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */
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#define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */
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#define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */
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#define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */
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#define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */
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#define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */
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#define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */
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#define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */
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#define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */
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#define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */
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#define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */
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/* request register bit definitions */
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#define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */
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#define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */
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#define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */
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#define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */
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#define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */
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/* write single mask bit register bit definitions */
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#define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */
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#define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */
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#define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */
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#define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */
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#define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */
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/* read/write all mask bits register bit definitions */
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#define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */
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#define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */
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#define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */
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#define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */
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/* typedefs */
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#define W83C553F_DMA1_CS 0x8
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#define W83C553F_DMA1_WR 0x9
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#define W83C553F_DMA1_WSMB 0xA
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#define W83C553F_DMA1_WM 0xB
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#define W83C553F_DMA1_CBP 0xC
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#define W83C553F_DMA1_MC 0xD
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#define W83C553F_DMA1_CM 0xE
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#define W83C553F_DMA1_RWAMB 0xF
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#define W83C553F_DMA2_CS 0x10
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#define W83C553F_DMA2_WR 0x12
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#define W83C553F_DMA2_WSMB 0x14
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#define W83C553F_DMA2_WM 0x16
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#define W83C553F_DMA2_CBP 0x18
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#define W83C553F_DMA2_MC 0x1A
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#define W83C553F_DMA2_CM 0x1C
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#define W83C553F_DMA2_RWAMB 0x1E
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void initialise_w83c553f(void);
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