mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-22 10:59:43 +09:00
6d97dc10a8
To i.MX6SX/UL, two ethernet interfaces are supported. Add ENET2 clock support: 1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed. To value 1, only i.MX6SX/UL can pass the check. 2. Modify board code who use this api to follow new api prototype. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> |
||
---|---|---|
.. | ||
aristainetos2.cfg | ||
aristainetos-v1.c | ||
aristainetos-v2.c | ||
aristainetos.c | ||
aristainetos.cfg | ||
axi.cfg | ||
clocks2.cfg | ||
clocks.cfg | ||
ddr-setup2.cfg | ||
ddr-setup.cfg | ||
Kconfig | ||
MAINTAINERS | ||
Makefile | ||
mt41j128M.cfg | ||
nt5cc256m16cp.cfg |