Shengzhou Liu 0d3972cfcd fsl/ddr: Add workaround for ERRATUM_A009942 ... During the receive data training, the DDRC may complete on a non-optimal setting that could lead to data corruption or initialization failure. Workaround: before setting MEM_EN, set DEBUG_29 register with specific value for different data rates. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>		2016-01-25 08:24:14 -08:00
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altera	ddr: altera: Init the rule ID in debug code	2016-01-16 07:07:22 +01:00
fsl	fsl/ddr: Add workaround for ERRATUM_A009942	2016-01-25 08:24:14 -08:00
marvell	mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BIT	2016-01-14 14:08:59 +01:00