mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-31 14:28:52 +09:00
![]() During the receive data training, the DDRC may complete on a non-optimal setting that could lead to data corruption or initialization failure. Workaround: before setting MEM_EN, set DEBUG_29 register with specific value for different data rates. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com> |
||
---|---|---|
.. | ||
clock.h | ||
config.h | ||
cpu.h | ||
fdt.h | ||
fsl_serdes.h | ||
immap_lsch2.h | ||
immap_lsch3.h | ||
imx-regs.h | ||
ls2080a_stream_id.h | ||
mmu.h | ||
mp.h | ||
ns_access.h | ||
soc.h | ||
speed.h |