mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 19:56:18 +09:00
163 lines
3.7 KiB
C
163 lines
3.7 KiB
C
/*
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* (C) Copyright 2005
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* BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
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*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include "asm/m5282.h"
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#include "VCxK.h"
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int checkboard (void)
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{
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puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
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#if (TEXT_BASE == CFG_INT_FLASH_BASE)
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puts (" Boot from Internal FLASH\n");
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#endif
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return 0;
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}
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phys_size_t initdram (int board_type)
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{
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int size, i;
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size = 0;
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MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6
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| MCFSDRAMC_DCR_RC ((15 * CFG_CLK) >> 4);
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#ifdef CFG_SDRAM_BASE0
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MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE0)
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| MCFSDRAMC_DACR_CASL (1)
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| MCFSDRAMC_DACR_CBM (3)
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| MCFSDRAMC_DACR_PS_16;
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MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
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MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
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*(unsigned short *) (CFG_SDRAM_BASE0) = 0xA5A5;
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MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
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for (i = 0; i < 2000; i++)
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asm (" nop");
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mbar_writeLong (MCFSDRAMC_DACR0,
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mbar_readLong (MCFSDRAMC_DACR0) | MCFSDRAMC_DACR_IMRS);
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*(unsigned int *) (CFG_SDRAM_BASE0 + 0x220) = 0xA5A5;
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size += CFG_SDRAM_SIZE * 1024 * 1024;
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#endif
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#ifdef CFG_SDRAM_BASE1
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MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE1)
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| MCFSDRAMC_DACR_CASL (1)
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| MCFSDRAMC_DACR_CBM (3)
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| MCFSDRAMC_DACR_PS_16;
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MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
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MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
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*(unsigned short *) (CFG_SDRAM_BASE1) = 0xA5A5;
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MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
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for (i = 0; i < 2000; i++)
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asm (" nop");
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MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
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*(unsigned int *) (CFG_SDRAM_BASE1 + 0x220) = 0xA5A5;
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size += CFG_SDRAM_SIZE1 * 1024 * 1024;
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#endif
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return size;
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}
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#if defined(CFG_DRAM_TEST)
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int testdram (void)
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{
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uint *pstart = (uint *) CFG_MEMTEST_START;
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uint *pend = (uint *) CFG_MEMTEST_END;
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uint *p;
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printf("SDRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("SDRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("SDRAM test passed.\n");
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return 0;
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}
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#endif
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int misc_init_r(void)
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{
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init_vcxk();
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return 1;
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}
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/*---------------------------------------------------------------------------*/
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int do_vcimage (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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int rcode = 0;
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ulong source;
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switch (argc) {
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case 2:
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source = simple_strtoul(argv[1],NULL,16);
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vcxk_loadimage(source);
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rcode = 0;
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break;
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default:
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printf ("Usage:\n%s\n", cmdtp->usage);
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rcode = 1;
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break;
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}
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return rcode;
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}
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/***************************************************/
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U_BOOT_CMD(
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vcimage, 2, 0, do_vcimage,
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"vcimage - loads an image to Display\n",
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"vcimage addr\n"
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);
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/* EOF EB+MCF-EV123c */
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