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![wdenk](/assets/img/avatar_default.png)
- Add support for Altera FPGA ACEX1K * Patches by Thomas Lange, 09 Oct 2003: - Endian swap ATA identity for all big endian CPUs, not just PPC - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize args to linux - add support for dbau1x00 board (MIPS32)
548 lines
16 KiB
C
548 lines
16 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
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* Copyright (C) 2000 Silicon Graphics, Inc.
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* Modified for further R[236]000 support by Paul M. Antoine, 1996.
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* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 2003 Maciej W. Rozycki
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*/
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#ifndef _ASM_MIPSREGS_H
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#define _ASM_MIPSREGS_H
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#if 0
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#include <linux/linkage.h>
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#endif
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/*
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* The following macros are especially useful for __asm__
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* inline assembler.
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*/
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#ifndef __STR
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#define __STR(x) #x
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#endif
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#ifndef STR
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#define STR(x) __STR(x)
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#endif
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/*
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* Coprocessor 0 register names
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*/
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#define CP0_INDEX $0
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#define CP0_RANDOM $1
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#define CP0_ENTRYLO0 $2
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#define CP0_ENTRYLO1 $3
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#define CP0_CONF $3
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#define CP0_CONTEXT $4
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#define CP0_PAGEMASK $5
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#define CP0_WIRED $6
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#define CP0_INFO $7
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#define CP0_BADVADDR $8
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#define CP0_COUNT $9
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#define CP0_ENTRYHI $10
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#define CP0_COMPARE $11
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#define CP0_STATUS $12
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#define CP0_CAUSE $13
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#define CP0_EPC $14
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#define CP0_PRID $15
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#define CP0_CONFIG $16
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#define CP0_LLADDR $17
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#define CP0_WATCHLO $18
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#define CP0_WATCHHI $19
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#define CP0_XCONTEXT $20
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#define CP0_FRAMEMASK $21
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#define CP0_DIAGNOSTIC $22
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#define CP0_PERFORMANCE $25
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#define CP0_ECC $26
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#define CP0_CACHEERR $27
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#define CP0_TAGLO $28
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#define CP0_TAGHI $29
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#define CP0_ERROREPC $30
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/*
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* R4640/R4650 cp0 register names. These registers are listed
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* here only for completeness; without MMU these CPUs are not useable
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* by Linux. A future ELKS port might take make Linux run on them
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* though ...
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*/
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#define CP0_IBASE $0
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#define CP0_IBOUND $1
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#define CP0_DBASE $2
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#define CP0_DBOUND $3
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#define CP0_CALG $17
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#define CP0_IWATCH $18
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#define CP0_DWATCH $19
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/*
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* Coprocessor 0 Set 1 register names
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*/
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#define CP0_S1_DERRADDR0 $26
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#define CP0_S1_DERRADDR1 $27
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#define CP0_S1_INTCONTROL $20
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/*
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* Coprocessor 1 (FPU) register names
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*/
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#define CP1_REVISION $0
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#define CP1_STATUS $31
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/*
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* FPU Status Register Values
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*/
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/*
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* Status Register Values
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*/
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#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
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#define FPU_CSR_COND 0x00800000 /* $fcc0 */
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#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
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#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
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#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
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#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
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#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
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#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
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#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
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#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
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/*
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* X the exception cause indicator
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* E the exception enable
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* S the sticky/flag bit
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*/
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#define FPU_CSR_ALL_X 0x0003f000
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#define FPU_CSR_UNI_X 0x00020000
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#define FPU_CSR_INV_X 0x00010000
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#define FPU_CSR_DIV_X 0x00008000
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#define FPU_CSR_OVF_X 0x00004000
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#define FPU_CSR_UDF_X 0x00002000
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#define FPU_CSR_INE_X 0x00001000
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#define FPU_CSR_ALL_E 0x00000f80
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#define FPU_CSR_INV_E 0x00000800
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#define FPU_CSR_DIV_E 0x00000400
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#define FPU_CSR_OVF_E 0x00000200
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#define FPU_CSR_UDF_E 0x00000100
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#define FPU_CSR_INE_E 0x00000080
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#define FPU_CSR_ALL_S 0x0000007c
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#define FPU_CSR_INV_S 0x00000040
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#define FPU_CSR_DIV_S 0x00000020
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#define FPU_CSR_OVF_S 0x00000010
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#define FPU_CSR_UDF_S 0x00000008
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#define FPU_CSR_INE_S 0x00000004
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/* rounding mode */
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#define FPU_CSR_RN 0x0 /* nearest */
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#define FPU_CSR_RZ 0x1 /* towards zero */
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#define FPU_CSR_RU 0x2 /* towards +Infinity */
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#define FPU_CSR_RD 0x3 /* towards -Infinity */
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/*
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* Values for PageMask register
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*/
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#include <linux/config.h>
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#ifdef CONFIG_CPU_VR41XX
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#define PM_1K 0x00000000
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#define PM_4K 0x00001800
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#define PM_16K 0x00007800
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#define PM_64K 0x0001f800
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#define PM_256K 0x0007f800
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#else
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#define PM_4K 0x00000000
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#define PM_16K 0x00006000
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#define PM_64K 0x0001e000
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#define PM_256K 0x0007e000
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#define PM_1M 0x001fe000
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#define PM_4M 0x007fe000
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#define PM_16M 0x01ffe000
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#endif
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/*
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* Values used for computation of new tlb entries
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*/
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#define PL_4K 12
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#define PL_16K 14
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#define PL_64K 16
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#define PL_256K 18
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#define PL_1M 20
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#define PL_4M 22
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#define PL_16M 24
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/*
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* Macros to access the system control coprocessor
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*/
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#define read_32bit_cp0_register(source) \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set\treorder\n\t" \
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"mfc0\t%0,"STR(source)"\n\t" \
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".set\tpop" \
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: "=r" (__res)); \
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__res;})
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#define read_32bit_cp0_set1_register(source) \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set\treorder\n\t" \
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"cfc0\t%0,"STR(source)"\n\t" \
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".set\tpop" \
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: "=r" (__res)); \
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__res;})
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/*
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* For now use this only with interrupts disabled!
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*/
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#define read_64bit_cp0_register(source) \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tmips3\n\t" \
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"dmfc0\t%0,"STR(source)"\n\t" \
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".set\tmips0" \
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: "=r" (__res)); \
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__res;})
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#define write_32bit_cp0_register(register,value) \
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__asm__ __volatile__( \
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"mtc0\t%0,"STR(register)"\n\t" \
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"nop" \
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: : "r" (value));
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#define write_32bit_cp0_set1_register(register,value) \
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__asm__ __volatile__( \
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"ctc0\t%0,"STR(register)"\n\t" \
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"nop" \
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: : "r" (value));
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#define write_64bit_cp0_register(register,value) \
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__asm__ __volatile__( \
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".set\tmips3\n\t" \
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"dmtc0\t%0,"STR(register)"\n\t" \
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".set\tmips0" \
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: : "r" (value))
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/*
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* This should be changed when we get a compiler that support the MIPS32 ISA.
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*/
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#define read_mips32_cp0_config1() \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tnoreorder\n\t" \
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".set\tnoat\n\t" \
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".word\t0x40018001\n\t" \
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"move\t%0,$1\n\t" \
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".set\tat\n\t" \
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".set\treorder" \
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:"=r" (__res)); \
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__res;})
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#define tlb_write_indexed() \
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__asm__ __volatile__( \
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".set noreorder\n\t" \
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"tlbwi\n\t" \
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".set reorder")
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/*
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* R4x00 interrupt enable / cause bits
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*/
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#define IE_SW0 (1<< 8)
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#define IE_SW1 (1<< 9)
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#define IE_IRQ0 (1<<10)
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#define IE_IRQ1 (1<<11)
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#define IE_IRQ2 (1<<12)
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#define IE_IRQ3 (1<<13)
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#define IE_IRQ4 (1<<14)
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#define IE_IRQ5 (1<<15)
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/*
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* R4x00 interrupt cause bits
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*/
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#define C_SW0 (1<< 8)
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#define C_SW1 (1<< 9)
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#define C_IRQ0 (1<<10)
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#define C_IRQ1 (1<<11)
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#define C_IRQ2 (1<<12)
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#define C_IRQ3 (1<<13)
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#define C_IRQ4 (1<<14)
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#define C_IRQ5 (1<<15)
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#ifndef _LANGUAGE_ASSEMBLY
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/*
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* Manipulate the status register.
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* Mostly used to access the interrupt bits.
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*/
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#define __BUILD_SET_CP0(name,register) \
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extern __inline__ unsigned int \
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set_cp0_##name(unsigned int set) \
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{ \
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unsigned int res; \
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\
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res = read_32bit_cp0_register(register); \
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res |= set; \
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write_32bit_cp0_register(register, res); \
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\
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return res; \
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} \
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\
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extern __inline__ unsigned int \
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clear_cp0_##name(unsigned int clear) \
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{ \
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unsigned int res; \
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\
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res = read_32bit_cp0_register(register); \
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res &= ~clear; \
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write_32bit_cp0_register(register, res); \
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\
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return res; \
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} \
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\
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extern __inline__ unsigned int \
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change_cp0_##name(unsigned int change, unsigned int new) \
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{ \
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unsigned int res; \
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\
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res = read_32bit_cp0_register(register); \
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res &= ~change; \
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res |= (new & change); \
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if(change) \
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write_32bit_cp0_register(register, res); \
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\
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return res; \
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}
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__BUILD_SET_CP0(status,CP0_STATUS)
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__BUILD_SET_CP0(cause,CP0_CAUSE)
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__BUILD_SET_CP0(config,CP0_CONFIG)
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#endif /* defined (_LANGUAGE_ASSEMBLY) */
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/*
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* Bitfields in the R4xx0 cp0 status register
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*/
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#define ST0_IE 0x00000001
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#define ST0_EXL 0x00000002
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#define ST0_ERL 0x00000004
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#define ST0_KSU 0x00000018
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# define KSU_USER 0x00000010
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# define KSU_SUPERVISOR 0x00000008
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# define KSU_KERNEL 0x00000000
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#define ST0_UX 0x00000020
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#define ST0_SX 0x00000040
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#define ST0_KX 0x00000080
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#define ST0_DE 0x00010000
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#define ST0_CE 0x00020000
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/*
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* Bitfields in the R[23]000 cp0 status register.
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*/
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#define ST0_IEC 0x00000001
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#define ST0_KUC 0x00000002
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#define ST0_IEP 0x00000004
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#define ST0_KUP 0x00000008
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#define ST0_IEO 0x00000010
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#define ST0_KUO 0x00000020
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/* bits 6 & 7 are reserved on R[23]000 */
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#define ST0_ISC 0x00010000
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#define ST0_SWC 0x00020000
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#define ST0_CM 0x00080000
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/*
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* Bits specific to the R4640/R4650
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*/
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#define ST0_UM (1 << 4)
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#define ST0_IL (1 << 23)
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#define ST0_DL (1 << 24)
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/*
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* Bitfields in the TX39 family CP0 Configuration Register 3
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*/
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#define TX39_CONF_ICS_SHIFT 19
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#define TX39_CONF_ICS_MASK 0x00380000
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#define TX39_CONF_ICS_1KB 0x00000000
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#define TX39_CONF_ICS_2KB 0x00080000
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#define TX39_CONF_ICS_4KB 0x00100000
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#define TX39_CONF_ICS_8KB 0x00180000
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#define TX39_CONF_ICS_16KB 0x00200000
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#define TX39_CONF_DCS_SHIFT 16
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#define TX39_CONF_DCS_MASK 0x00070000
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#define TX39_CONF_DCS_1KB 0x00000000
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#define TX39_CONF_DCS_2KB 0x00010000
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#define TX39_CONF_DCS_4KB 0x00020000
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#define TX39_CONF_DCS_8KB 0x00030000
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#define TX39_CONF_DCS_16KB 0x00040000
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#define TX39_CONF_CWFON 0x00004000
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#define TX39_CONF_WBON 0x00002000
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#define TX39_CONF_RF_SHIFT 10
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#define TX39_CONF_RF_MASK 0x00000c00
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#define TX39_CONF_DOZE 0x00000200
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#define TX39_CONF_HALT 0x00000100
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#define TX39_CONF_LOCK 0x00000080
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#define TX39_CONF_ICE 0x00000020
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#define TX39_CONF_DCE 0x00000010
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#define TX39_CONF_IRSIZE_SHIFT 2
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#define TX39_CONF_IRSIZE_MASK 0x0000000c
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#define TX39_CONF_DRSIZE_SHIFT 0
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#define TX39_CONF_DRSIZE_MASK 0x00000003
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/*
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* Status register bits available in all MIPS CPUs.
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*/
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#define ST0_IM 0x0000ff00
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#define STATUSB_IP0 8
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#define STATUSF_IP0 (1 << 8)
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#define STATUSB_IP1 9
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#define STATUSF_IP1 (1 << 9)
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#define STATUSB_IP2 10
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#define STATUSF_IP2 (1 << 10)
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#define STATUSB_IP3 11
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#define STATUSF_IP3 (1 << 11)
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#define STATUSB_IP4 12
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#define STATUSF_IP4 (1 << 12)
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#define STATUSB_IP5 13
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#define STATUSF_IP5 (1 << 13)
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#define STATUSB_IP6 14
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#define STATUSF_IP6 (1 << 14)
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#define STATUSB_IP7 15
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#define STATUSF_IP7 (1 << 15)
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#define STATUSB_IP8 0
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#define STATUSF_IP8 (1 << 0)
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#define STATUSB_IP9 1
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#define STATUSF_IP9 (1 << 1)
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#define STATUSB_IP10 2
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#define STATUSF_IP10 (1 << 2)
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#define STATUSB_IP11 3
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#define STATUSF_IP11 (1 << 3)
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#define STATUSB_IP12 4
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#define STATUSF_IP12 (1 << 4)
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#define STATUSB_IP13 5
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#define STATUSF_IP13 (1 << 5)
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#define STATUSB_IP14 6
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#define STATUSF_IP14 (1 << 6)
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#define STATUSB_IP15 7
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#define STATUSF_IP15 (1 << 7)
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#define ST0_CH 0x00040000
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#define ST0_SR 0x00100000
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#define ST0_BEV 0x00400000
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#define ST0_RE 0x02000000
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#define ST0_FR 0x04000000
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#define ST0_CU 0xf0000000
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#define ST0_CU0 0x10000000
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#define ST0_CU1 0x20000000
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#define ST0_CU2 0x40000000
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#define ST0_CU3 0x80000000
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#define ST0_XX 0x80000000 /* MIPS IV naming */
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/*
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* Bitfields and bit numbers in the coprocessor 0 cause register.
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*
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* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
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*/
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#define CAUSEB_EXCCODE 2
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#define CAUSEF_EXCCODE (31 << 2)
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#define CAUSEB_IP 8
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#define CAUSEF_IP (255 << 8)
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#define CAUSEB_IP0 8
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#define CAUSEF_IP0 (1 << 8)
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#define CAUSEB_IP1 9
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#define CAUSEF_IP1 (1 << 9)
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#define CAUSEB_IP2 10
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#define CAUSEF_IP2 (1 << 10)
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#define CAUSEB_IP3 11
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#define CAUSEF_IP3 (1 << 11)
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#define CAUSEB_IP4 12
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#define CAUSEF_IP4 (1 << 12)
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#define CAUSEB_IP5 13
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#define CAUSEF_IP5 (1 << 13)
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#define CAUSEB_IP6 14
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#define CAUSEF_IP6 (1 << 14)
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#define CAUSEB_IP7 15
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#define CAUSEF_IP7 (1 << 15)
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#define CAUSEB_IV 23
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#define CAUSEF_IV (1 << 23)
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#define CAUSEB_CE 28
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#define CAUSEF_CE (3 << 28)
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#define CAUSEB_BD 31
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#define CAUSEF_BD (1 << 31)
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/*
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* Bits in the coprozessor 0 config register.
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*/
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#define CONF_CM_CACHABLE_NO_WA 0
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#define CONF_CM_CACHABLE_WA 1
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#define CONF_CM_UNCACHED 2
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#define CONF_CM_CACHABLE_NONCOHERENT 3
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#define CONF_CM_CACHABLE_CE 4
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#define CONF_CM_CACHABLE_COW 5
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#define CONF_CM_CACHABLE_CUW 6
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#define CONF_CM_CACHABLE_ACCELERATED 7
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#define CONF_CM_CMASK 7
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#define CONF_DB (1 << 4)
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#define CONF_IB (1 << 5)
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#define CONF_SC (1 << 17)
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#define CONF_AC (1 << 23)
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#define CONF_HALT (1 << 25)
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/*
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* R10000 performance counter definitions.
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*
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* FIXME: The R10000 performance counter opens a nice way to implement CPU
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* time accounting with a precission of one cycle. I don't have
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* R10000 silicon but just a manual, so ...
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*/
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/*
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* Events counted by counter #0
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*/
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#define CE0_CYCLES 0
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#define CE0_INSN_ISSUED 1
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#define CE0_LPSC_ISSUED 2
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#define CE0_S_ISSUED 3
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#define CE0_SC_ISSUED 4
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#define CE0_SC_FAILED 5
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#define CE0_BRANCH_DECODED 6
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#define CE0_QW_WB_SECONDARY 7
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#define CE0_CORRECTED_ECC_ERRORS 8
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#define CE0_ICACHE_MISSES 9
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#define CE0_SCACHE_I_MISSES 10
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#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
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#define CE0_EXT_INTERVENTIONS_REQ 12
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#define CE0_EXT_INVALIDATE_REQ 13
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#define CE0_VIRTUAL_COHERENCY_COND 14
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#define CE0_INSN_GRADUATED 15
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/*
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* Events counted by counter #1
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*/
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#define CE1_CYCLES 0
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#define CE1_INSN_GRADUATED 1
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#define CE1_LPSC_GRADUATED 2
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#define CE1_S_GRADUATED 3
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#define CE1_SC_GRADUATED 4
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#define CE1_FP_INSN_GRADUATED 5
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#define CE1_QW_WB_PRIMARY 6
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#define CE1_TLB_REFILL 7
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#define CE1_BRANCH_MISSPREDICTED 8
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#define CE1_DCACHE_MISS 9
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#define CE1_SCACHE_D_MISSES 10
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#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
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#define CE1_EXT_INTERVENTION_HITS 12
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|
#define CE1_EXT_INVALIDATE_REQ 13
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#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
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|
#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
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|
|
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/*
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* These flags define in which priviledge mode the counters count events
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|
*/
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#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
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#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
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#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
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#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
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#endif /* _ASM_MIPSREGS_H */
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