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https://github.com/brain-hackers/u-boot-brain
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f605079041
Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/fsl_serdes.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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static u8 serdes_cfg_tbl[][4] = {
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[0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
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[0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1},
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[0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1},
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[0x99] = {XFI_FM1_MAC1, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
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[0x46] = {PCIE1, PCIE1, PCIE2, SATA1},
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[0x47] = {PCIE1, PCIE1, PCIE2, SGMII_FM1_DTSEC1},
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[0x56] = {PCIE1, PCIE3, PCIE2, SATA1},
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[0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1},
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[0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
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[0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1},
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[0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
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[0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
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SGMII_2500_FM1_DTSEC1},
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[0x77] = {PCIE1, SGMII_2500_FM1_DTSEC3, PCIE2, SGMII_FM1_DTSEC1},
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[0x7F] = {PCIE1, SGMII_2500_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
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SGMII_2500_FM1_DTSEC1},
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[0x119] = {AURORA, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
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[0x135] = {AURORA, SGMII_2500_FM1_DTSEC3, PCIE2, PCIE1},
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};
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
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{
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return serdes_cfg_tbl[cfg][lane];
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}
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int is_serdes_prtcl_valid(int serdes, u32 prtcl)
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{
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int i;
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if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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for (i = 0; i < 4; i++) {
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if (serdes_cfg_tbl[prtcl][i] != NONE)
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return 1;
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}
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return 0;
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}
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