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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
540 lines
12 KiB
C
540 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
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* Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
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*
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* Derived from the code for
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* Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <env.h>
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#include <i2c.h>
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#include <init.h>
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#include <log.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <dm/uclass.h>
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#include <fdt_support.h>
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#include <time.h>
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#include <linux/bitops.h>
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#include <u-boot/crc.h>
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# include <atsha204a-i2c.h>
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#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
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#include <../serdes/a38x/high_speed_env_spec.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
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#define OMNIA_I2C_MCU_CHIP_ADDR 0x2a
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#define OMNIA_I2C_MCU_CHIP_LEN 1
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#define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54
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#define OMNIA_I2C_EEPROM_CHIP_LEN 2
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#define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
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enum mcu_commands {
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CMD_GET_STATUS_WORD = 0x01,
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CMD_GET_RESET = 0x09,
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CMD_WATCHDOG_STATE = 0x0b,
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};
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enum status_word_bits {
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CARD_DET_STSBIT = 0x0010,
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MSATA_IND_STSBIT = 0x0020,
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};
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#define OMNIA_ATSHA204_OTP_VERSION 0
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#define OMNIA_ATSHA204_OTP_SERIAL 1
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#define OMNIA_ATSHA204_OTP_MAC0 3
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#define OMNIA_ATSHA204_OTP_MAC1 4
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/*
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* Those values and defines are taken from the Marvell U-Boot version
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* "u-boot-2013.01-2014_T3.0"
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*/
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#define OMNIA_GPP_OUT_ENA_LOW \
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(~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
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BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
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BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
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#define OMNIA_GPP_OUT_ENA_MID \
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(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
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BIT(16) | BIT(17) | BIT(18)))
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#define OMNIA_GPP_OUT_VAL_LOW 0x0
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#define OMNIA_GPP_OUT_VAL_MID 0x0
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#define OMNIA_GPP_POL_LOW 0x0
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#define OMNIA_GPP_POL_MID 0x0
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static struct serdes_map board_serdes_map_pex[] = {
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{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
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{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
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{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
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{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
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};
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static struct serdes_map board_serdes_map_sata[] = {
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{SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
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{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
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{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
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};
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static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
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uint offset_len)
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{
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struct udevice *bus, *dev;
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int ret;
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ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
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if (ret) {
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printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
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OMNIA_I2C_BUS_NAME, ret);
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return NULL;
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}
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ret = i2c_get_chip(bus, addr, offset_len, &dev);
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if (ret) {
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printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
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name, ret);
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return NULL;
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}
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return dev;
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}
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static int omnia_mcu_read(u8 cmd, void *buf, int len)
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{
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struct udevice *chip;
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chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
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OMNIA_I2C_MCU_CHIP_LEN);
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if (!chip)
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return -ENODEV;
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return dm_i2c_read(chip, cmd, buf, len);
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}
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#ifndef CONFIG_SPL_BUILD
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static int omnia_mcu_write(u8 cmd, const void *buf, int len)
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{
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struct udevice *chip;
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chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
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OMNIA_I2C_MCU_CHIP_LEN);
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if (!chip)
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return -ENODEV;
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return dm_i2c_write(chip, cmd, buf, len);
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}
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static bool disable_mcu_watchdog(void)
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{
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int ret;
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puts("Disabling MCU watchdog... ");
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ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
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if (ret) {
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printf("omnia_mcu_write failed: %i\n", ret);
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return false;
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}
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puts("disabled\n");
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return true;
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}
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#endif
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static bool omnia_detect_sata(void)
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{
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int ret;
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u16 stsword;
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puts("MiniPCIe/mSATA card detection... ");
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ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
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if (ret) {
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printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
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ret);
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return false;
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}
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if (!(stsword & CARD_DET_STSBIT)) {
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puts("none\n");
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return false;
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}
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if (stsword & MSATA_IND_STSBIT)
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puts("mSATA\n");
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else
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puts("MiniPCIe\n");
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return stsword & MSATA_IND_STSBIT ? true : false;
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}
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int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
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{
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if (omnia_detect_sata()) {
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*serdes_map_array = board_serdes_map_sata;
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*count = ARRAY_SIZE(board_serdes_map_sata);
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} else {
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*serdes_map_array = board_serdes_map_pex;
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*count = ARRAY_SIZE(board_serdes_map_pex);
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}
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return 0;
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}
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struct omnia_eeprom {
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u32 magic;
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u32 ramsize;
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char region[4];
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u32 crc;
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};
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static bool omnia_read_eeprom(struct omnia_eeprom *oep)
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{
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struct udevice *chip;
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u32 crc;
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int ret;
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chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
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OMNIA_I2C_EEPROM_CHIP_LEN);
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if (!chip)
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return false;
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ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
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if (ret) {
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printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
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return false;
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}
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if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
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printf("bad EEPROM magic number (%08x, should be %08x)\n",
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oep->magic, OMNIA_I2C_EEPROM_MAGIC);
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return false;
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}
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crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
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if (crc != oep->crc) {
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printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
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oep->crc, crc);
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return false;
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}
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return true;
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}
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static int omnia_get_ram_size_gb(void)
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{
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static int ram_size;
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struct omnia_eeprom oep;
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if (!ram_size) {
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/* Get the board config from EEPROM */
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if (omnia_read_eeprom(&oep)) {
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debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
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if (oep.ramsize == 0x2)
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ram_size = 2;
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else
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ram_size = 1;
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} else {
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/* Hardcoded fallback */
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puts("Memory config from EEPROM read failed!\n");
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puts("Falling back to default 1 GiB!\n");
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ram_size = 1;
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}
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}
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return ram_size;
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}
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/*
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* Define the DDR layout / topology here in the board file. This will
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* be used by the DDR3 init code in the SPL U-Boot version to configure
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* the DDR3 controller.
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*/
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static struct mv_ddr_topology_map board_topology_map_1g = {
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
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{ { { {0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0} },
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SPEED_BIN_DDR_1600K, /* speed_bin */
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MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
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MV_DDR_DIE_CAP_4GBIT, /* mem_size */
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MV_DDR_FREQ_800, /* frequency */
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0, 0, /* cas_wl cas_l */
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MV_DDR_TEMP_NORMAL, /* temperature */
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MV_DDR_TIM_2T} }, /* timing */
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BUS_MASK_32BIT, /* Busses mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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{ {0} }, /* raw spd data */
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{0} /* timing parameters */
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};
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static struct mv_ddr_topology_map board_topology_map_2g = {
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
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{ { { {0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0} },
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SPEED_BIN_DDR_1600K, /* speed_bin */
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MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
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MV_DDR_DIE_CAP_8GBIT, /* mem_size */
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MV_DDR_FREQ_800, /* frequency */
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0, 0, /* cas_wl cas_l */
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MV_DDR_TEMP_NORMAL, /* temperature */
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MV_DDR_TIM_2T} }, /* timing */
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BUS_MASK_32BIT, /* Busses mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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{ {0} }, /* raw spd data */
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{0} /* timing parameters */
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};
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struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
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{
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if (omnia_get_ram_size_gb() == 2)
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return &board_topology_map_2g;
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else
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return &board_topology_map_1g;
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}
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#ifndef CONFIG_SPL_BUILD
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static int set_regdomain(void)
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{
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struct omnia_eeprom oep;
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char rd[3] = {' ', ' ', 0};
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if (omnia_read_eeprom(&oep))
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memcpy(rd, &oep.region, 2);
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else
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puts("EEPROM regdomain read failed.\n");
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printf("Regdomain set to %s\n", rd);
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return env_set("regdomain", rd);
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}
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/*
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* default factory reset bootcommand on Omnia first sets all the front LEDs
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* to green and then tries to load the rescue image from SPI flash memory and
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* boot it
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*/
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#define OMNIA_FACTORY_RESET_BOOTCMD \
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"i2c dev 2; " \
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"i2c mw 0x2a.1 0x3 0x1c 1; " \
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"i2c mw 0x2a.1 0x4 0x1c 1; " \
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"mw.l 0x01000000 0x00ff000c; " \
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"i2c write 0x01000000 0x2a.1 0x5 4 -s; " \
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"setenv bootargs \"earlyprintk console=ttyS0,115200" \
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" omniarescue=$omnia_reset\"; " \
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"sf probe; " \
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"sf read 0x1000000 0x100000 0x700000; " \
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"bootm 0x1000000; " \
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"bootz 0x1000000"
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static void handle_reset_button(void)
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{
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int ret;
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u8 reset_status;
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ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
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if (ret) {
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printf("omnia_mcu_read failed: %i, reset status unknown!\n",
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ret);
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return;
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}
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env_set_ulong("omnia_reset", reset_status);
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if (reset_status) {
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printf("RESET button was pressed, overwriting bootcmd!\n");
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env_set("bootcmd", OMNIA_FACTORY_RESET_BOOTCMD);
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}
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}
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#endif
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int board_early_init_f(void)
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{
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/* Configure MPP */
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writel(0x11111111, MVEBU_MPP_BASE + 0x00);
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writel(0x11111111, MVEBU_MPP_BASE + 0x04);
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writel(0x11244011, MVEBU_MPP_BASE + 0x08);
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writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
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writel(0x22200002, MVEBU_MPP_BASE + 0x10);
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writel(0x30042022, MVEBU_MPP_BASE + 0x14);
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writel(0x55550555, MVEBU_MPP_BASE + 0x18);
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writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
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/* Set GPP Out value */
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writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
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writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
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/* Set GPP Polarity */
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writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
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writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
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/* Set GPP Out Enable */
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writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
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writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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#ifndef CONFIG_SPL_BUILD
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disable_mcu_watchdog();
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#endif
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return 0;
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}
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int board_late_init(void)
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{
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#ifndef CONFIG_SPL_BUILD
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set_regdomain();
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handle_reset_button();
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#endif
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pci_init();
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return 0;
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}
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static struct udevice *get_atsha204a_dev(void)
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{
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static struct udevice *dev;
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if (dev)
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return dev;
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if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
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puts("Cannot find ATSHA204A on I2C bus!\n");
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dev = NULL;
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}
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return dev;
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}
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int checkboard(void)
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{
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u32 version_num, serial_num;
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int err = 1;
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struct udevice *dev = get_atsha204a_dev();
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if (dev) {
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err = atsha204a_wakeup(dev);
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if (err)
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goto out;
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err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
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OMNIA_ATSHA204_OTP_VERSION,
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(u8 *)&version_num);
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if (err)
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goto out;
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err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
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OMNIA_ATSHA204_OTP_SERIAL,
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(u8 *)&serial_num);
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if (err)
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goto out;
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atsha204a_sleep(dev);
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}
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out:
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printf("Turris Omnia:\n");
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printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
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if (err)
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printf(" Serial Number: unknown\n");
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else
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printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num),
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be32_to_cpu(serial_num));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void increment_mac(u8 *mac)
|
|
{
|
|
int i;
|
|
|
|
for (i = 5; i >= 3; i--) {
|
|
mac[i] += 1;
|
|
if (mac[i])
|
|
break;
|
|
}
|
|
}
|
|
|
|
int misc_init_r(void)
|
|
{
|
|
int err;
|
|
struct udevice *dev = get_atsha204a_dev();
|
|
u8 mac0[4], mac1[4], mac[6];
|
|
|
|
if (!dev)
|
|
goto out;
|
|
|
|
err = atsha204a_wakeup(dev);
|
|
if (err)
|
|
goto out;
|
|
|
|
err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
|
|
OMNIA_ATSHA204_OTP_MAC0, mac0);
|
|
if (err)
|
|
goto out;
|
|
|
|
err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
|
|
OMNIA_ATSHA204_OTP_MAC1, mac1);
|
|
if (err)
|
|
goto out;
|
|
|
|
atsha204a_sleep(dev);
|
|
|
|
mac[0] = mac0[1];
|
|
mac[1] = mac0[2];
|
|
mac[2] = mac0[3];
|
|
mac[3] = mac1[1];
|
|
mac[4] = mac1[2];
|
|
mac[5] = mac1[3];
|
|
|
|
if (is_valid_ethaddr(mac))
|
|
eth_env_set_enetaddr("eth1addr", mac);
|
|
|
|
increment_mac(mac);
|
|
|
|
if (is_valid_ethaddr(mac))
|
|
eth_env_set_enetaddr("eth2addr", mac);
|
|
|
|
increment_mac(mac);
|
|
|
|
if (is_valid_ethaddr(mac))
|
|
eth_env_set_enetaddr("ethaddr", mac);
|
|
|
|
out:
|
|
return 0;
|
|
}
|
|
|