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![Suneel Garapati](/assets/img/avatar_default.png)
Adds support for NAND controllers found on OcteonTX or OcteonTX2 SoC platforms. Also includes driver to support Hardware ECC using BCH HW engine found on these platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
426 lines
9.8 KiB
C
426 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#include <dm.h>
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#include <dm/of_access.h>
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#include <malloc.h>
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#include <memalign.h>
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#include <nand.h>
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#include <pci.h>
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#include <pci_ids.h>
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#include <time.h>
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#include <linux/bitfield.h>
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#include <linux/ctype.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/ioport.h>
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#include <linux/libfdt.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand_bch.h>
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#include <linux/mtd/nand_ecc.h>
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#include <asm/io.h>
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#include <asm/types.h>
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#include <asm/dma-mapping.h>
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#include <asm/arch/clock.h>
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#include "octeontx_bch.h"
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#ifdef DEBUG
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# undef CONFIG_LOGLEVEL
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# define CONFIG_LOGLEVEL 8
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#endif
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LIST_HEAD(octeontx_bch_devices);
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static unsigned int num_vfs = BCH_NR_VF;
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static void *bch_pf;
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static void *bch_vf;
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static void *token;
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static bool bch_pf_initialized;
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static bool bch_vf_initialized;
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static int pci_enable_sriov(struct udevice *dev, int nr_virtfn)
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{
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int ret;
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ret = pci_sriov_init(dev, nr_virtfn);
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if (ret)
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printf("%s(%s): pci_sriov_init returned %d\n", __func__,
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dev->name, ret);
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return ret;
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}
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void *octeontx_bch_getv(void)
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{
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if (!bch_vf)
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return NULL;
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if (bch_vf_initialized && bch_pf_initialized)
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return bch_vf;
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else
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return NULL;
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}
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void octeontx_bch_putv(void *token)
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{
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bch_vf_initialized = !!token;
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bch_vf = token;
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}
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void *octeontx_bch_getp(void)
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{
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return token;
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}
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void octeontx_bch_putp(void *token)
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{
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bch_pf = token;
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bch_pf_initialized = !!token;
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}
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static int do_bch_init(struct bch_device *bch)
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{
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return 0;
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}
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static void bch_reset(struct bch_device *bch)
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{
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writeq(1, bch->reg_base + BCH_CTL);
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mdelay(2);
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}
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static void bch_disable(struct bch_device *bch)
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{
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writeq(~0ull, bch->reg_base + BCH_ERR_INT_ENA_W1C);
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writeq(~0ull, bch->reg_base + BCH_ERR_INT);
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bch_reset(bch);
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}
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static u32 bch_check_bist_status(struct bch_device *bch)
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{
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return readq(bch->reg_base + BCH_BIST_RESULT);
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}
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static int bch_device_init(struct bch_device *bch)
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{
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u64 bist;
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int rc;
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debug("%s: Resetting...\n", __func__);
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/* Reset the PF when probed first */
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bch_reset(bch);
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debug("%s: Checking BIST...\n", __func__);
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/* Check BIST status */
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bist = (u64)bch_check_bist_status(bch);
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if (bist) {
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dev_err(dev, "BCH BIST failed with code 0x%llx\n", bist);
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return -ENODEV;
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}
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/* Get max VQs/VFs supported by the device */
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bch->max_vfs = pci_sriov_get_totalvfs(bch->dev);
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debug("%s: %d vfs\n", __func__, bch->max_vfs);
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if (num_vfs > bch->max_vfs) {
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dev_warn(dev, "Num of VFs to enable %d is greater than max available. Enabling %d VFs.\n",
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num_vfs, bch->max_vfs);
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num_vfs = bch->max_vfs;
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}
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bch->vfs_enabled = bch->max_vfs;
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/* Get number of VQs/VFs to be enabled */
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/* TODO: Get CLK frequency */
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/* Reset device parameters */
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debug("%s: Doing initialization\n", __func__);
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rc = do_bch_init(bch);
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return rc;
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}
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static int bch_sriov_configure(struct udevice *dev, int numvfs)
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{
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struct bch_device *bch = dev_get_priv(dev);
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int ret = -EBUSY;
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debug("%s(%s, %d), bch: %p, vfs_in_use: %d, enabled: %d\n", __func__,
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dev->name, numvfs, bch, bch->vfs_in_use, bch->vfs_enabled);
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if (bch->vfs_in_use)
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goto exit;
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ret = 0;
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if (numvfs > 0) {
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debug("%s: Enabling sriov\n", __func__);
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ret = pci_enable_sriov(dev, numvfs);
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if (ret == 0) {
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bch->flags |= BCH_FLAG_SRIOV_ENABLED;
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ret = numvfs;
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bch->vfs_enabled = numvfs;
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}
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}
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debug("VFs enabled: %d\n", ret);
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exit:
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debug("%s: Returning %d\n", __func__, ret);
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return ret;
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}
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static int octeontx_pci_bchpf_probe(struct udevice *dev)
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{
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struct bch_device *bch;
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int ret;
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debug("%s(%s)\n", __func__, dev->name);
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bch = dev_get_priv(dev);
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if (!bch)
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return -ENOMEM;
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bch->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
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bch->dev = dev;
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debug("%s: base address: %p\n", __func__, bch->reg_base);
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ret = bch_device_init(bch);
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if (ret) {
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printf("%s(%s): init returned %d\n", __func__, dev->name, ret);
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return ret;
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}
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INIT_LIST_HEAD(&bch->list);
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list_add(&bch->list, &octeontx_bch_devices);
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token = (void *)dev;
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debug("%s: Configuring SRIOV\n", __func__);
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bch_sriov_configure(dev, num_vfs);
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debug("%s: Done.\n", __func__);
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octeontx_bch_putp(bch);
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return 0;
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}
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static const struct pci_device_id octeontx_bchpf_pci_id_table[] = {
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{ PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_BCH) },
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{},
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};
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static const struct pci_device_id octeontx_bchvf_pci_id_table[] = {
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{ PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_BCHVF)},
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{},
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};
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/**
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* Given a data block calculate the ecc data and fill in the response
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*
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* @param[in] block 8-byte aligned pointer to data block to calculate ECC
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* @param block_size Size of block in bytes, must be a multiple of two.
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* @param bch_level Number of errors that must be corrected. The number of
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* parity bytes is equal to ((15 * bch_level) + 7) / 8.
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* Must be 4, 8, 16, 24, 32, 40, 48, 56, 60 or 64.
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* @param[out] ecc 8-byte aligned pointer to where ecc data should go
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* @param[in] resp pointer to where responses will be written.
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*
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* @return Zero on success, negative on failure.
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*/
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int octeontx_bch_encode(struct bch_vf *vf, dma_addr_t block, u16 block_size,
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u8 bch_level, dma_addr_t ecc, dma_addr_t resp)
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{
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union bch_cmd cmd;
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int rc;
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memset(&cmd, 0, sizeof(cmd));
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cmd.s.cword.ecc_gen = eg_gen;
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cmd.s.cword.ecc_level = bch_level;
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cmd.s.cword.size = block_size;
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cmd.s.oword.ptr = ecc;
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cmd.s.iword.ptr = block;
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cmd.s.rword.ptr = resp;
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rc = octeontx_cmd_queue_write(QID_BCH, 1,
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sizeof(cmd) / sizeof(uint64_t), cmd.u);
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if (rc)
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return -1;
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octeontx_bch_write_doorbell(1, vf);
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return 0;
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}
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/**
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* Given a data block and ecc data correct the data block
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*
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* @param[in] block_ecc_in 8-byte aligned pointer to data block with ECC
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* data concatenated to the end to correct
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* @param block_size Size of block in bytes, must be a multiple of
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* two.
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* @param bch_level Number of errors that must be corrected. The
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* number of parity bytes is equal to
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* ((15 * bch_level) + 7) / 8.
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* Must be 4, 8, 16, 24, 32, 40, 48, 56, 60 or 64.
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* @param[out] block_out 8-byte aligned pointer to corrected data buffer.
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* This should not be the same as block_ecc_in.
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* @param[in] resp pointer to where responses will be written.
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*
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* @return Zero on success, negative on failure.
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*/
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int octeontx_bch_decode(struct bch_vf *vf, dma_addr_t block_ecc_in,
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u16 block_size, u8 bch_level,
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dma_addr_t block_out, dma_addr_t resp)
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{
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union bch_cmd cmd;
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int rc;
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memset(&cmd, 0, sizeof(cmd));
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cmd.s.cword.ecc_gen = eg_correct;
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cmd.s.cword.ecc_level = bch_level;
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cmd.s.cword.size = block_size;
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cmd.s.oword.ptr = block_out;
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cmd.s.iword.ptr = block_ecc_in;
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cmd.s.rword.ptr = resp;
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rc = octeontx_cmd_queue_write(QID_BCH, 1,
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sizeof(cmd) / sizeof(uint64_t), cmd.u);
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if (rc)
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return -1;
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octeontx_bch_write_doorbell(1, vf);
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return 0;
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}
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EXPORT_SYMBOL(octeontx_bch_decode);
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int octeontx_bch_wait(struct bch_vf *vf, union bch_resp *resp,
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dma_addr_t handle)
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{
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ulong start = get_timer(0);
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__iormb(); /* HW is updating *resp */
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while (!resp->s.done && get_timer(start) < 10)
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__iormb(); /* HW is updating *resp */
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if (resp->s.done)
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return 0;
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return -ETIMEDOUT;
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}
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struct bch_q octeontx_bch_q[QID_MAX];
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static int octeontx_cmd_queue_initialize(struct udevice *dev, int queue_id,
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int max_depth, int fpa_pool,
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int pool_size)
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{
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/* some params are for later merge with CPT or cn83xx */
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struct bch_q *q = &octeontx_bch_q[queue_id];
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unsigned long paddr;
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u64 *chunk_buffer;
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int chunk = max_depth + 1;
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int i, size;
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if ((unsigned int)queue_id >= QID_MAX)
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return -EINVAL;
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if (max_depth & chunk) /* must be 2^N - 1 */
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return -EINVAL;
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size = NQS * chunk * sizeof(u64);
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chunk_buffer = dma_alloc_coherent(size, &paddr);
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if (!chunk_buffer)
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return -ENOMEM;
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q->base_paddr = paddr;
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q->dev = dev;
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q->index = 0;
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q->max_depth = max_depth;
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q->pool_size_m1 = pool_size;
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q->base_vaddr = chunk_buffer;
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for (i = 0; i < NQS; i++) {
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u64 *ixp;
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int inext = (i + 1) * chunk - 1;
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int j = (i + 1) % NQS;
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int jnext = j * chunk;
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dma_addr_t jbase = q->base_paddr + jnext * sizeof(u64);
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ixp = &chunk_buffer[inext];
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*ixp = jbase;
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}
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return 0;
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}
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static int octeontx_pci_bchvf_probe(struct udevice *dev)
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{
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struct bch_vf *vf;
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union bch_vqx_ctl ctl;
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union bch_vqx_cmd_buf cbuf;
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int err;
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debug("%s(%s)\n", __func__, dev->name);
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vf = dev_get_priv(dev);
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if (!vf)
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return -ENOMEM;
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vf->dev = dev;
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/* Map PF's configuration registers */
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vf->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
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debug("%s: reg base: %p\n", __func__, vf->reg_base);
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err = octeontx_cmd_queue_initialize(dev, QID_BCH, QDEPTH - 1, 0,
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sizeof(union bch_cmd) * QDEPTH);
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if (err) {
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dev_err(dev, "octeontx_cmd_queue_initialize() failed\n");
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goto release;
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}
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ctl.u = readq(vf->reg_base + BCH_VQX_CTL(0));
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cbuf.u = 0;
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cbuf.s.ldwb = 1;
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cbuf.s.dfb = 1;
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cbuf.s.size = QDEPTH;
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writeq(cbuf.u, vf->reg_base + BCH_VQX_CMD_BUF(0));
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writeq(ctl.u, vf->reg_base + BCH_VQX_CTL(0));
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writeq(octeontx_bch_q[QID_BCH].base_paddr,
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vf->reg_base + BCH_VQX_CMD_PTR(0));
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octeontx_bch_putv(vf);
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debug("%s: bch vf initialization complete\n", __func__);
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if (octeontx_bch_getv())
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return octeontx_pci_nand_deferred_probe();
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return -1;
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release:
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return err;
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}
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static int octeontx_pci_bchpf_remove(struct udevice *dev)
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{
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struct bch_device *bch = dev_get_priv(dev);
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bch_disable(bch);
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return 0;
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}
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U_BOOT_DRIVER(octeontx_pci_bchpf) = {
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.name = BCHPF_DRIVER_NAME,
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.id = UCLASS_MISC,
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.probe = octeontx_pci_bchpf_probe,
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.remove = octeontx_pci_bchpf_remove,
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.priv_auto_alloc_size = sizeof(struct bch_device),
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.flags = DM_FLAG_OS_PREPARE,
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};
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U_BOOT_DRIVER(octeontx_pci_bchvf) = {
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.name = BCHVF_DRIVER_NAME,
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.id = UCLASS_MISC,
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.probe = octeontx_pci_bchvf_probe,
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.priv_auto_alloc_size = sizeof(struct bch_vf),
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};
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U_BOOT_PCI_DEVICE(octeontx_pci_bchpf, octeontx_bchpf_pci_id_table);
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U_BOOT_PCI_DEVICE(octeontx_pci_bchvf, octeontx_bchvf_pci_id_table);
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