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https://github.com/brain-hackers/u-boot-brain
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0c9075e9ad
Add code to set up the Local Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
58 lines
1.6 KiB
C
58 lines
1.6 KiB
C
/*
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* From coreboot file of same name
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <asm/msr.h>
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#include <asm/io.h>
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#include <asm/lapic.h>
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#include <asm/post.h>
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void lapic_setup(void)
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{
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#if NEED_LAPIC == 1
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/* Only Pentium Pro and later have those MSR stuff */
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debug("Setting up local apic: ");
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/* Enable the local apic */
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enable_lapic();
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/*
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* Set Task Priority to 'accept all'.
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*/
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lapic_write_around(LAPIC_TASKPRI,
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lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
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/* Put the local apic in virtual wire mode */
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lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) &
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~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
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lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0) &
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~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
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LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
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LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
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LAPIC_DELIVERY_MODE_MASK)) |
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(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
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LAPIC_DELIVERY_MODE_EXTINT));
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lapic_write_around(LAPIC_LVT1, (lapic_read_around(LAPIC_LVT1) &
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~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
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LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
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LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
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LAPIC_DELIVERY_MODE_MASK)) |
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(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
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LAPIC_DELIVERY_MODE_NMI));
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debug("apic_id: 0x%02lx, ", lapicid());
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#else /* !NEED_LLAPIC */
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/* Only Pentium Pro and later have those MSR stuff */
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debug("Disabling local apic: ");
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disable_lapic();
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#endif /* !NEED_LAPIC */
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debug("done.\n");
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post_code(POST_LAPIC);
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}
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