mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-20 18:17:59 +09:00
260777fc23
Add support for CDCE913/925/937/949 family of devices. These are modular PLL-based low cost, high performance, programmable clock synthesizers, multipliers and dividers. They generate up to 9 output clocks from a single input frequency. The initial version of the driver does not support programming of the PLLs, and thus they run in the bypass mode only. The code is loosely based on the linux kernel cdce9xx driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
48 lines
1.7 KiB
Makefile
48 lines
1.7 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (c) 2015 Google, Inc
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
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obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
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obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
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obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o
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obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o
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obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
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obj-y += analogbits/
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obj-y += imx/
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obj-y += tegra/
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obj-$(CONFIG_ARCH_ASPEED) += aspeed/
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obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
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obj-$(CONFIG_ARCH_MESON) += meson/
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obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_ARCH_SOCFPGA) += altera/
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obj-$(CONFIG_CLK_AT91) += at91/
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obj-$(CONFIG_CLK_MVEBU) += mvebu/
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obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
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obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
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obj-$(CONFIG_CLK_EXYNOS) += exynos/
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obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
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obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
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obj-$(CONFIG_CLK_OWL) += owl/
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obj-$(CONFIG_CLK_RENESAS) += renesas/
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obj-$(CONFIG_CLK_SIFIVE) += sifive/
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obj-$(CONFIG_ARCH_SUNXI) += sunxi/
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obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
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obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
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obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
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obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
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obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
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obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
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obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
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obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
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obj-$(CONFIG_SANDBOX) += clk_sandbox.o
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obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
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obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
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obj-$(CONFIG_STM32H7) += clk_stm32h7.o
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obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o
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obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
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obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
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