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https://github.com/brain-hackers/u-boot-brain
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![]() This patch adds workaround for ARM errata 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> |
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.. | ||
cpu | ||
dts | ||
imx-common | ||
include | ||
lib | ||
mach-at91 | ||
mach-davinci | ||
mach-highbank | ||
mach-keystone | ||
mach-kirkwood | ||
mach-nomadik | ||
mach-orion5x | ||
mach-tegra | ||
mach-versatile | ||
mvebu-common | ||
config.mk | ||
Kconfig | ||
Kconfig.debug | ||
Makefile |