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862e2e75e8
RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
8 lines
154 B
Plaintext
8 lines
154 B
Plaintext
CONFIG_RISCV=y
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CONFIG_TARGET_QEMU_VIRT=y
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CONFIG_ARCH_RV64I=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_DISPLAY_CPUINFO=y
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CONFIG_DISPLAY_BOARDINFO=y
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CONFIG_OF_BOARD=y
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