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https://github.com/brain-hackers/u-boot-brain
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![Stefano Babic](/assets/img/avatar_default.png)
Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Akshay Bhat <akshaybhat@timesys.com> CC: Ken Lin <Ken.Lin@advantech.com.tw> CC: Marek Vasut <marek.vasut@gmail.com> CC: Heiko Schocher <hs@denx.de> CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> CC: Christian Gmeiner <christian.gmeiner@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Patrick Bruenn <p.bruenn@beckhoff.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Nikita Kiryanov <nikita@compulab.co.il> CC: Otavio Salvador <otavio@ossystems.com.br> CC: "Eric Bénard" <eric@eukrea.com> CC: Jagan Teki <jagan@amarulasolutions.com> CC: Ye Li <ye.li@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Adrian Alonso <adrian.alonso@nxp.com> CC: Alison Wang <b18965@freescale.com> CC: Tim Harvey <tharvey@gateworks.com> CC: Martin Donnelly <martin.donnelly@ge.com> CC: Marcin Niestroj <m.niestroj@grinn-global.com> CC: Lukasz Majewski <lukma@denx.de> CC: Adam Ford <aford173@gmail.com> CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr> CC: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Soeren Moch <smoch@web.de> CC: Richard Hu <richard.hu@technexion.com> CC: Wig Cheng <wig.cheng@technexion.com> CC: Vanessa Maegima <vanessa.maegima@nxp.com> CC: Max Krummenacher <max.krummenacher@toradex.com> CC: Stefan Agner <stefan.agner@toradex.com> CC: Markus Niebel <Markus.Niebel@tq-group.com> CC: Breno Lima <breno.lima@nxp.com> CC: Francesco Montefoschi <francesco.montefoschi@udoo.org> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Scott Wood <oss@buserror.net> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Anatolij Gustschin <agust@denx.de> CC: Simon Glass <sjg@chromium.org> CC: "Andrew F. Davis" <afd@ti.com> CC: "Łukasz Majewski" <l.majewski@samsung.com> CC: Patrice Chotard <patrice.chotard@st.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Hans de Goede <hdegoede@redhat.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stephen Warren <swarren@nvidia.com> CC: Andre Przywara <andre.przywara@arm.com> CC: "Álvaro Fernández Rojas" <noltari@gmail.com> CC: York Sun <york.sun@nxp.com> CC: Xiaoliang Yang <xiaoliang.yang@nxp.com> CC: Chen-Yu Tsai <wens@csie.org> CC: George McCollister <george.mccollister@gmail.com> CC: Sven Ebenfeld <sven.ebenfeld@gmail.com> CC: Filip Brozovic <fbrozovic@gmail.com> CC: Petr Kulhavy <brain@jikos.cz> CC: Eric Nelson <eric@nelint.com> CC: Bai Ping <ping.bai@nxp.com> CC: Anson Huang <Anson.Huang@nxp.com> CC: Sanchayan Maity <maitysanchayan@gmail.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Patrick Delaunay <patrick.delaunay@st.com> CC: Gary Bisson <gary.bisson@boundarydevices.com> CC: Alexander Graf <agraf@suse.de> CC: u-boot@lists.denx.de Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
93 lines
2.6 KiB
INI
93 lines
2.6 KiB
INI
/*
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* Aries M53 DRAM init values
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* Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#include <asm/mach-imx/imximage.cfg>
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/* image version */
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IMAGE_VERSION 2
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/* Boot Offset 0x400, valid for both SD and NAND boot. */
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BOOT_OFFSET FLASH_OFFSET_STANDARD
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */
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DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */
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DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */
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DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */
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DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */
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DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */
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DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */
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DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */
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DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */
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DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */
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DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */
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DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */
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DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */
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DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */
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DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */
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DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */
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DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */
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DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */
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DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */
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DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */
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DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */
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DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */
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DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */
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DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */
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/* ESDCTL */
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DATA 4 0x63fd9088 0x32383535
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DATA 4 0x63fd9090 0x40383538
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DATA 4 0x63fd907c 0x0136014d
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DATA 4 0x63fd9080 0x01510141
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DATA 4 0x63fd9018 0x00011740
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DATA 4 0x63fd9000 0xc3190000
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DATA 4 0x63fd900c 0x555952e3
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DATA 4 0x63fd9010 0xb68e8b63
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DATA 4 0x63fd9014 0x01ff00db
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DATA 4 0x63fd902c 0x000026d2
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DATA 4 0x63fd9030 0x009f0e21
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DATA 4 0x63fd9008 0x12273030
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DATA 4 0x63fd9004 0x0002002d
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DATA 4 0x63fd901c 0x00008032
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DATA 4 0x63fd901c 0x00008033
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DATA 4 0x63fd901c 0x00028031
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DATA 4 0x63fd901c 0x092080b0
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DATA 4 0x63fd901c 0x04008040
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DATA 4 0x63fd901c 0x0000803a
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DATA 4 0x63fd901c 0x0000803b
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DATA 4 0x63fd901c 0x00028039
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DATA 4 0x63fd901c 0x09208138
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DATA 4 0x63fd901c 0x04008048
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DATA 4 0x63fd9020 0x00001800
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DATA 4 0x63fd9040 0x04b80003
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DATA 4 0x63fd9058 0x00022227
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DATA 4 0x63fd901c 0x00000000
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