mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
ceee07b658
Updates the NAND code to match Linux v4.6. The previous sync was from
Linux v4.1 in commit d3963721d9.
Note that none of the individual NAND drivers tracked Linux closely
enough to be synced themselves, other than manually applying a few
cross-tree changes.
Signed-off-by: Scott Wood <oss@buserror.net>
Tested-by: Heiko Schocher <hs@denx.de>
352 lines
8.5 KiB
C
352 lines
8.5 KiB
C
/*
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* (C) Copyright 2009
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* Magnus Lilja <lilja.magnus@gmail.com>
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*
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* (C) Copyright 2008
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* Maxim Artamonov, <scn1874 at yandex.ru>
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*
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* (C) Copyright 2006-2008
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* Stefan Roese, DENX Software Engineering, sr at denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <nand.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/io.h>
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#include "mxc_nand.h"
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#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
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static struct mxc_nand_regs *const nfc = (void *)NFC_BASE_ADDR;
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#elif defined(MXC_NFC_V3_2)
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static struct mxc_nand_regs *const nfc = (void *)NFC_BASE_ADDR_AXI;
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static struct mxc_nand_ip_regs *const nfc_ip = (void *)NFC_BASE_ADDR;
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#endif
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static void nfc_wait_ready(void)
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{
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uint32_t tmp;
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#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
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while (!(readnfc(&nfc->config2) & NFC_V1_V2_CONFIG2_INT))
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;
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/* Reset interrupt flag */
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tmp = readnfc(&nfc->config2);
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tmp &= ~NFC_V1_V2_CONFIG2_INT;
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writenfc(tmp, &nfc->config2);
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#elif defined(MXC_NFC_V3_2)
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while (!(readnfc(&nfc_ip->ipc) & NFC_V3_IPC_INT))
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;
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/* Reset interrupt flag */
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tmp = readnfc(&nfc_ip->ipc);
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tmp &= ~NFC_V3_IPC_INT;
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writenfc(tmp, &nfc_ip->ipc);
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#endif
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}
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static void nfc_nand_init(void)
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{
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#if defined(MXC_NFC_V3_2)
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int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
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int tmp;
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tmp = (readnfc(&nfc_ip->config2) & ~(NFC_V3_CONFIG2_SPAS_MASK |
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NFC_V3_CONFIG2_EDC_MASK | NFC_V3_CONFIG2_PS_MASK)) |
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NFC_V3_CONFIG2_SPAS(CONFIG_SYS_NAND_OOBSIZE / 2) |
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NFC_V3_CONFIG2_INT_MSK | NFC_V3_CONFIG2_ECC_EN |
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NFC_V3_CONFIG2_ONE_CYCLE;
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if (CONFIG_SYS_NAND_PAGE_SIZE == 4096)
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tmp |= NFC_V3_CONFIG2_PS_4096;
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else if (CONFIG_SYS_NAND_PAGE_SIZE == 2048)
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tmp |= NFC_V3_CONFIG2_PS_2048;
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else if (CONFIG_SYS_NAND_PAGE_SIZE == 512)
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tmp |= NFC_V3_CONFIG2_PS_512;
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/*
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* if spare size is larger that 16 bytes per 512 byte hunk
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* then use 8 symbol correction instead of 4
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*/
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if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16)
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tmp |= NFC_V3_CONFIG2_ECC_MODE_8;
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else
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tmp &= ~NFC_V3_CONFIG2_ECC_MODE_8;
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writenfc(tmp, &nfc_ip->config2);
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tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
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NFC_V3_CONFIG3_NO_SDMA |
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NFC_V3_CONFIG3_RBB_MODE |
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NFC_V3_CONFIG3_SBB(6) | /* Reset default */
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NFC_V3_CONFIG3_ADD_OP(0);
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#ifndef CONFIG_SYS_NAND_BUSWIDTH_16
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tmp |= NFC_V3_CONFIG3_FW8;
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#endif
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writenfc(tmp, &nfc_ip->config3);
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writenfc(0, &nfc_ip->delay_line);
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#elif defined(MXC_NFC_V2_1)
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int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
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int config1;
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writenfc(CONFIG_SYS_NAND_OOBSIZE / 2, &nfc->spare_area_size);
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/* unlocking RAM Buff */
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writenfc(0x2, &nfc->config);
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/* hardware ECC checking and correct */
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config1 = readnfc(&nfc->config1) | NFC_V1_V2_CONFIG1_ECC_EN |
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NFC_V1_V2_CONFIG1_INT_MSK | NFC_V2_CONFIG1_ONE_CYCLE |
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NFC_V2_CONFIG1_FP_INT;
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/*
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* if spare size is larger that 16 bytes per 512 byte hunk
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* then use 8 symbol correction instead of 4
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*/
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if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16)
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config1 &= ~NFC_V2_CONFIG1_ECC_MODE_4;
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else
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config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
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writenfc(config1, &nfc->config1);
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#elif defined(MXC_NFC_V1)
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/* unlocking RAM Buff */
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writenfc(0x2, &nfc->config);
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/* hardware ECC checking and correct */
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writenfc(NFC_V1_V2_CONFIG1_ECC_EN | NFC_V1_V2_CONFIG1_INT_MSK,
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&nfc->config1);
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#endif
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}
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static void nfc_nand_command(unsigned short command)
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{
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writenfc(command, &nfc->flash_cmd);
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writenfc(NFC_CMD, &nfc->operation);
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nfc_wait_ready();
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}
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static void nfc_nand_address(unsigned short address)
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{
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writenfc(address, &nfc->flash_addr);
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writenfc(NFC_ADDR, &nfc->operation);
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nfc_wait_ready();
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}
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static void nfc_nand_page_address(unsigned int page_address)
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{
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unsigned int page_count;
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nfc_nand_address(0x00);
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/* code only for large page flash */
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if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
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nfc_nand_address(0x00);
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page_count = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
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if (page_address <= page_count) {
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page_count--; /* transform 0x01000000 to 0x00ffffff */
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do {
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nfc_nand_address(page_address & 0xff);
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page_address = page_address >> 8;
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page_count = page_count >> 8;
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} while (page_count);
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}
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nfc_nand_address(0x00);
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}
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static void nfc_nand_data_output(void)
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{
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#ifdef NAND_MXC_2K_MULTI_CYCLE
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int i;
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#endif
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#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
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writenfc(0, &nfc->buf_addr);
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#elif defined(MXC_NFC_V3_2)
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int config1 = readnfc(&nfc->config1);
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config1 &= ~NFC_V3_CONFIG1_RBA_MASK;
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writenfc(config1, &nfc->config1);
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#endif
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writenfc(NFC_OUTPUT, &nfc->operation);
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nfc_wait_ready();
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#ifdef NAND_MXC_2K_MULTI_CYCLE
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/*
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* This NAND controller requires multiple input commands
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* for pages larger than 512 bytes.
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*/
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for (i = 1; i < CONFIG_SYS_NAND_PAGE_SIZE / 512; i++) {
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writenfc(i, &nfc->buf_addr);
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writenfc(NFC_OUTPUT, &nfc->operation);
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nfc_wait_ready();
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}
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#endif
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}
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static int nfc_nand_check_ecc(void)
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{
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#if defined(MXC_NFC_V1)
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u16 ecc_status = readw(&nfc->ecc_status_result);
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return (ecc_status & 0x3) == 2 || (ecc_status >> 2) == 2;
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#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
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u32 ecc_status = readl(&nfc->ecc_status_result);
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int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
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int err_limit = CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16 ? 8 : 4;
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int subpages = CONFIG_SYS_NAND_PAGE_SIZE / 512;
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do {
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if ((ecc_status & 0xf) > err_limit)
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return 1;
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ecc_status >>= 4;
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} while (--subpages);
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return 0;
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#endif
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}
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static void nfc_nand_read_page(unsigned int page_address)
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{
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/* read in first 0 buffer */
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#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
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writenfc(0, &nfc->buf_addr);
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#elif defined(MXC_NFC_V3_2)
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int config1 = readnfc(&nfc->config1);
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config1 &= ~NFC_V3_CONFIG1_RBA_MASK;
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writenfc(config1, &nfc->config1);
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#endif
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nfc_nand_command(NAND_CMD_READ0);
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nfc_nand_page_address(page_address);
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if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
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nfc_nand_command(NAND_CMD_READSTART);
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nfc_nand_data_output(); /* fill the main buffer 0 */
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}
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static int nfc_read_page(unsigned int page_address, unsigned char *buf)
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{
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int i;
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u32 *src;
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u32 *dst;
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nfc_nand_read_page(page_address);
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if (nfc_nand_check_ecc())
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return -EBADMSG;
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src = (u32 *)&nfc->main_area[0][0];
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dst = (u32 *)buf;
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/* main copy loop from NAND-buffer to SDRAM memory */
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for (i = 0; i < CONFIG_SYS_NAND_PAGE_SIZE / 4; i++) {
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writel(readl(src), dst);
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src++;
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dst++;
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}
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return 0;
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}
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static int is_badblock(int pagenumber)
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{
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int page = pagenumber;
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u32 badblock;
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u32 *src;
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/* Check the first two pages for bad block markers */
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for (page = pagenumber; page < pagenumber + 2; page++) {
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nfc_nand_read_page(page);
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src = (u32 *)&nfc->spare_area[0][0];
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/*
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* IMPORTANT NOTE: The nand flash controller uses a non-
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* standard layout for large page devices. This can
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* affect the position of the bad block marker.
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*/
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/* Get the bad block marker */
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badblock = readl(&src[CONFIG_SYS_NAND_BAD_BLOCK_POS / 4]);
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badblock >>= 8 * (CONFIG_SYS_NAND_BAD_BLOCK_POS % 4);
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badblock &= 0xff;
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/* bad block marker verify */
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if (badblock != 0xff)
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return 1; /* potential bad block */
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}
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return 0;
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}
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int nand_spl_load_image(uint32_t from, unsigned int size, void *buf)
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{
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int i;
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unsigned int page;
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unsigned int maxpages = CONFIG_SYS_NAND_SIZE /
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CONFIG_SYS_NAND_PAGE_SIZE;
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nfc_nand_init();
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/* Convert to page number */
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page = from / CONFIG_SYS_NAND_PAGE_SIZE;
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i = 0;
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size = roundup(size, CONFIG_SYS_NAND_PAGE_SIZE);
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while (i < size / CONFIG_SYS_NAND_PAGE_SIZE) {
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if (nfc_read_page(page, buf) < 0)
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return -1;
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page++;
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i++;
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buf = buf + CONFIG_SYS_NAND_PAGE_SIZE;
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/*
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* Check if we have crossed a block boundary, and if so
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* check for bad block.
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*/
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if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) {
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/*
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* Yes, new block. See if this block is good. If not,
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* loop until we find a good block.
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*/
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while (is_badblock(page)) {
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page = page + CONFIG_SYS_NAND_PAGE_COUNT;
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/* Check i we've reached the end of flash. */
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if (page >= maxpages)
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return -1;
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}
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}
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}
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return 0;
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}
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#ifndef CONFIG_SPL_FRAMEWORK
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/*
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* The main entry for NAND booting. It's necessary that SDRAM is already
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* configured and available since this code loads the main U-Boot image
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* from NAND into SDRAM and starts it from there.
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*/
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void nand_boot(void)
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{
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__attribute__((noreturn)) void (*uboot)(void);
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/*
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* CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
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* be aligned to full pages
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*/
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if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
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CONFIG_SYS_NAND_U_BOOT_SIZE,
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(uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
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/* Copy from NAND successful, start U-Boot */
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uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
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uboot();
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} else {
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/* Unrecoverable error when copying from NAND */
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hang();
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}
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}
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#endif
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void nand_init(void) {}
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void nand_deselect(void) {}
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