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https://github.com/brain-hackers/u-boot-brain
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6f6b7cfa89
This converts the following to Kconfig: CONFIG_CONS_INDEX We have existing entries for this option in a number of places, with different guards on them. They're also sometimes used for things not directly inside of the serial driver. First, introduce a new symbol to guard the use of CONFIG_CONS_INDEX, so that in the case where we don't need this for the serial driver, but for some other use, we can still do it. Next, consolidate all of these into the single entry in drivers/serial/Kconfig. Finally, introduce CONS_INDEX_[023456] so that we can imply a correct value here to make the defconfig side of this smaller. Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Rework a lot of the logic here, such that I took authorship from Adam, but kept his S-o-B line] Signed-off-by: Tom Rini <trini@konsulko.com>
156 lines
4.6 KiB
C
156 lines
4.6 KiB
C
/*
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* (C) Copyright 2004
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* Texas Instruments.
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* Richard Woodruff <r-woodruff2@ti.com>
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* Kshitij Gupta <kshitij@ti.com>
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*
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* Configuration settings for the phyCORE-i.MX31 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/imx-regs.h>
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/* High Level Configuration Options */
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#define CONFIG_MX31 /* This is a mx31 */
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#define CONFIG_MX31_CLK32 32000
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
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/*
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* Hardware drivers
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_BASE
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/***********************************************************
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* Command definition
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***********************************************************/
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 192.168.23.168
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#define CONFIG_SERVERIP 192.168.23.2
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
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"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
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"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
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"bootargs_flash=setenv bootargs $(bootargs) " \
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"root=/dev/mtdblock2 rootfstype=jffs2\0" \
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"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
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"bootcmd=run bootcmd_net\0" \
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"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \
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"tftpboot 0x80000000 $(uimage);bootm\0" \
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"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \
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"bootm 0x80000000\0" \
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"unlock=yes\0" \
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"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
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"prg_uboot=tftpboot 0x80000000 $(uboot);" \
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"protect off 0xa0000000 +0x20000;" \
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"erase 0xa0000000 +0x20000;" \
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"cp.b 0x80000000 0xa0000000 $(filesize)\0" \
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"prg_kernel=tftpboot 0x80000000 $(uimage);" \
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"erase 0xa0040000 +0x180000;" \
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"cp.b 0x80000000 0xa0040000 $(filesize)\0" \
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"prg_jffs2=tftpboot 0x80000000 $(jffs2);" \
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"erase 0xa01c0000 0xa1ffffff;" \
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"cp.b 0x80000000 0xa01c0000 $(filesize)\0" \
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"videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \
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"pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \
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"sync:1241513985,vmode:0\0"
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x10000
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#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 0x80000000
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#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_GBL_DATA_OFFSET)
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/*
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_FLASH_BASE 0xa0000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */
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/* Monitor at beginning of flash */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_ENV_OFFSET 0x00 /* env. starts here */
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#define CONFIG_ENV_SIZE 4096
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */
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/*
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* CFI FLASH driver setup
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*/
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#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
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#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
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#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
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/*
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* Timeout for Flash Erase and Flash Write
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* timeout values are in ticks
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*/
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#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ)
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/*
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* JFFS2 partitions
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*/
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#define CONFIG_JFFS2_DEV "nor0"
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/* EET platform additions */
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#ifdef CONFIG_TARGET_IMX31_PHYCORE_EET
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#define CONFIG_HARD_SPI
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#define CONFIG_S6E63D6
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#define CONFIG_VIDEO_MX3
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_BMP_16BPP
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#endif
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#endif /* __CONFIG_H */
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