mirror of
https://github.com/brain-hackers/u-boot-brain
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2f78eae506
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
25 lines
399 B
C
25 lines
399 B
C
/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_CONFIG_H_
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#define _ASM_CONFIG_H_
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#define CONFIG_SYS_GENERIC_GLOBAL_DATA
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#define CONFIG_LMB
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#define CONFIG_SYS_BOOT_RAMDISK_HIGH
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#ifdef CONFIG_ARM64
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#define CONFIG_PHYS_64BIT
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#define CONFIG_STATIC_RELA
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#endif
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#ifdef CONFIG_FSL_LSCH3
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#include <asm/arch-fsl-lsch3/config.h>
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#endif
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#endif
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