mirror of
https://github.com/brain-hackers/u-boot-brain
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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
270 lines
6.0 KiB
C
270 lines
6.0 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Microsemi SoCs pinctrl driver
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*
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* Author: <horatiu.vultur@microchip.com>
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* Copyright (c) 2019 Microsemi Corporation
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*/
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#include <common.h>
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#include <config.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/pinctrl.h>
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#include <dm/root.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <linux/io.h>
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#include <asm/gpio.h>
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#include <asm/system.h>
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#include "mscc-common.h"
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enum {
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FUNC_NONE,
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FUNC_GPIO,
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FUNC_IRQ0_IN,
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FUNC_IRQ0_OUT,
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FUNC_IRQ1_IN,
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FUNC_IRQ1_OUT,
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FUNC_MIIM1,
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FUNC_MIIM2,
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FUNC_PCI_WAKE,
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FUNC_PTP0,
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FUNC_PTP1,
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FUNC_PTP2,
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FUNC_PTP3,
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FUNC_PWM,
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FUNC_RCVRD_CLK0,
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FUNC_RCVRD_CLK1,
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FUNC_RCVRD_CLK2,
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FUNC_RCVRD_CLK3,
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FUNC_REF_CLK0,
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FUNC_REF_CLK1,
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FUNC_REF_CLK2,
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FUNC_REF_CLK3,
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FUNC_SFP0,
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FUNC_SFP1,
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FUNC_SFP2,
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FUNC_SFP3,
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FUNC_SFP4,
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FUNC_SFP5,
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FUNC_SFP6,
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FUNC_SFP7,
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FUNC_SFP8,
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FUNC_SFP9,
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FUNC_SFP10,
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FUNC_SFP11,
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FUNC_SFP12,
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FUNC_SFP13,
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FUNC_SFP14,
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FUNC_SFP15,
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FUNC_SIO,
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FUNC_SPI,
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FUNC_TACHO,
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FUNC_TWI,
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FUNC_TWI2,
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FUNC_TWI_SCL_M,
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FUNC_UART,
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FUNC_UART2,
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FUNC_MAX
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};
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static char * const servalt_function_names[] = {
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[FUNC_NONE] = "none",
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[FUNC_GPIO] = "gpio",
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[FUNC_IRQ0_IN] = "irq0_in",
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[FUNC_IRQ0_OUT] = "irq0_out",
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[FUNC_IRQ1_IN] = "irq1_in",
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[FUNC_IRQ1_OUT] = "irq1_out",
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[FUNC_MIIM1] = "miim1",
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[FUNC_MIIM2] = "miim2",
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[FUNC_PCI_WAKE] = "pci_wake",
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[FUNC_PTP0] = "ptp0",
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[FUNC_PTP1] = "ptp1",
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[FUNC_PTP2] = "ptp2",
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[FUNC_PTP3] = "ptp3",
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[FUNC_PWM] = "pwm",
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[FUNC_RCVRD_CLK0] = "rcvrd_clk0",
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[FUNC_RCVRD_CLK1] = "rcvrd_clk1",
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[FUNC_RCVRD_CLK2] = "rcvrd_clk2",
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[FUNC_RCVRD_CLK3] = "rcvrd_clk3",
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[FUNC_REF_CLK0] = "ref_clk0",
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[FUNC_REF_CLK1] = "ref_clk1",
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[FUNC_REF_CLK2] = "ref_clk2",
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[FUNC_REF_CLK3] = "ref_clk3",
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[FUNC_SFP0] = "sfp0",
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[FUNC_SFP1] = "sfp1",
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[FUNC_SFP2] = "sfp2",
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[FUNC_SFP3] = "sfp3",
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[FUNC_SFP4] = "sfp4",
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[FUNC_SFP5] = "sfp5",
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[FUNC_SFP6] = "sfp6",
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[FUNC_SFP7] = "sfp7",
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[FUNC_SFP8] = "sfp8",
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[FUNC_SFP9] = "sfp9",
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[FUNC_SFP10] = "sfp10",
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[FUNC_SFP11] = "sfp11",
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[FUNC_SFP12] = "sfp12",
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[FUNC_SFP13] = "sfp13",
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[FUNC_SFP14] = "sfp14",
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[FUNC_SFP15] = "sfp15",
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[FUNC_SIO] = "sio",
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[FUNC_SPI] = "spi",
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[FUNC_TACHO] = "tacho",
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[FUNC_TWI] = "twi",
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[FUNC_TWI2] = "twi2",
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[FUNC_TWI_SCL_M] = "twi_scl_m",
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[FUNC_UART] = "uart",
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[FUNC_UART2] = "uart2",
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};
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MSCC_P(0, SIO, NONE, NONE);
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MSCC_P(1, SIO, NONE, NONE);
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MSCC_P(2, SIO, NONE, NONE);
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MSCC_P(3, SIO, NONE, NONE);
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MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
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MSCC_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M);
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MSCC_P(6, UART, NONE, NONE);
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MSCC_P(7, UART, NONE, NONE);
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MSCC_P(8, SPI, SFP0, TWI_SCL_M);
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MSCC_P(9, PCI_WAKE, SFP1, SPI);
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MSCC_P(10, PTP0, SFP2, TWI_SCL_M);
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MSCC_P(11, PTP1, SFP3, TWI_SCL_M);
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MSCC_P(12, REF_CLK0, SFP4, TWI_SCL_M);
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MSCC_P(13, REF_CLK1, SFP5, TWI_SCL_M);
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MSCC_P(14, REF_CLK2, IRQ0_OUT, SPI);
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MSCC_P(15, REF_CLK3, IRQ1_OUT, SPI);
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MSCC_P(16, TACHO, SFP6, SPI);
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MSCC_P(17, PWM, NONE, TWI_SCL_M);
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MSCC_P(18, PTP2, SFP7, SPI);
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MSCC_P(19, PTP3, SFP8, SPI);
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MSCC_P(20, UART2, SFP9, SPI);
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MSCC_P(21, UART2, NONE, NONE);
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MSCC_P(22, MIIM1, SFP10, TWI2);
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MSCC_P(23, MIIM1, SFP11, TWI2);
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MSCC_P(24, TWI, NONE, NONE);
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MSCC_P(25, TWI, SFP12, TWI_SCL_M);
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MSCC_P(26, TWI_SCL_M, SFP13, SPI);
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MSCC_P(27, TWI_SCL_M, SFP14, SPI);
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MSCC_P(28, TWI_SCL_M, SFP15, SPI);
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MSCC_P(29, TWI_SCL_M, NONE, NONE);
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MSCC_P(30, TWI_SCL_M, NONE, NONE);
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MSCC_P(31, TWI_SCL_M, NONE, NONE);
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MSCC_P(32, TWI_SCL_M, NONE, NONE);
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MSCC_P(33, RCVRD_CLK0, NONE, NONE);
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MSCC_P(34, RCVRD_CLK1, NONE, NONE);
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MSCC_P(35, RCVRD_CLK2, NONE, NONE);
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MSCC_P(36, RCVRD_CLK3, NONE, NONE);
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#define SERVALT_PIN(n) { \
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.name = "GPIO_"#n, \
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.drv_data = &mscc_pin_##n \
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}
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static const struct mscc_pin_data servalt_pins[] = {
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SERVALT_PIN(0),
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SERVALT_PIN(1),
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SERVALT_PIN(2),
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SERVALT_PIN(3),
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SERVALT_PIN(4),
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SERVALT_PIN(5),
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SERVALT_PIN(6),
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SERVALT_PIN(7),
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SERVALT_PIN(8),
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SERVALT_PIN(9),
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SERVALT_PIN(10),
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SERVALT_PIN(11),
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SERVALT_PIN(12),
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SERVALT_PIN(13),
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SERVALT_PIN(14),
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SERVALT_PIN(15),
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SERVALT_PIN(16),
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SERVALT_PIN(17),
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SERVALT_PIN(18),
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SERVALT_PIN(19),
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SERVALT_PIN(20),
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SERVALT_PIN(21),
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SERVALT_PIN(22),
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SERVALT_PIN(23),
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SERVALT_PIN(24),
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SERVALT_PIN(25),
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SERVALT_PIN(26),
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SERVALT_PIN(27),
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SERVALT_PIN(28),
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SERVALT_PIN(29),
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SERVALT_PIN(30),
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SERVALT_PIN(31),
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SERVALT_PIN(32),
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SERVALT_PIN(33),
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SERVALT_PIN(34),
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SERVALT_PIN(35),
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SERVALT_PIN(36),
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};
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static const unsigned long servalt_gpios[] = {
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[MSCC_GPIO_OUT_SET] = 0x00,
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[MSCC_GPIO_OUT_CLR] = 0x08,
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[MSCC_GPIO_OUT] = 0x10,
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[MSCC_GPIO_IN] = 0x18,
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[MSCC_GPIO_OE] = 0x20,
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[MSCC_GPIO_INTR] = 0x28,
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[MSCC_GPIO_INTR_ENA] = 0x30,
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[MSCC_GPIO_INTR_IDENT] = 0x38,
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[MSCC_GPIO_ALT0] = 0x40,
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[MSCC_GPIO_ALT1] = 0x48,
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};
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static int servalt_gpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv;
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uc_priv = dev_get_uclass_priv(dev);
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uc_priv->bank_name = "servalt-gpio";
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uc_priv->gpio_count = ARRAY_SIZE(servalt_pins);
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return 0;
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}
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static struct driver servalt_gpio_driver = {
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.name = "servalt-gpio",
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.id = UCLASS_GPIO,
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.probe = servalt_gpio_probe,
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.ops = &mscc_gpio_ops,
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};
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static int servalt_pinctrl_probe(struct udevice *dev)
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{
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int ret;
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ret = mscc_pinctrl_probe(dev, FUNC_MAX, servalt_pins,
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ARRAY_SIZE(servalt_pins),
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servalt_function_names,
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servalt_gpios);
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if (ret)
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return ret;
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ret = device_bind(dev, &servalt_gpio_driver, "servalt-gpio", NULL,
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dev_ofnode(dev), NULL);
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if (ret)
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return ret;
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return 0;
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}
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static const struct udevice_id servalt_pinctrl_of_match[] = {
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{ .compatible = "mscc,servalt-pinctrl" },
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{},
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};
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U_BOOT_DRIVER(servalt_pinctrl) = {
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.name = "servalt-pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = of_match_ptr(servalt_pinctrl_of_match),
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.probe = servalt_pinctrl_probe,
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.priv_auto = sizeof(struct mscc_pinctrl),
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.ops = &mscc_pinctrl_ops,
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};
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