u-boot-brain/arch
Lokesh Vutla 40109f4d7e arm: mach-k3: Enable WA for R5F deadlock
On K3 devices there are 2 conditions where R5F can deadlock:
1.When software is performing series of store operations to
  cacheable write back/write allocate memory region and later
  on software execute barrier operation (DSB or DMB). R5F may
  hang at the barrier instruction.
2.When software is performing a mix of load and store operations
  within a tight loop and store operations are all writing to
  cacheable write back/write allocates memory regions, R5F may
  hang at one of the load instruction.

To avoid the above two conditions disable linefill optimization
inside Cortex R5F which will make R5F to only issue up to 2 cache
line fills at any point of time.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-03 09:47:11 -05:00
..
arc common: Move enable/disable_interrupts out of common.h 2019-12-02 18:25:01 -05:00
arm arm: mach-k3: Enable WA for R5F deadlock 2020-01-03 09:47:11 -05:00
m68k common: Move trap_init() out of common.h 2019-12-02 18:25:25 -05:00
microblaze common: Move enable/disable_interrupts out of common.h 2019-12-02 18:25:01 -05:00
mips Merge branch '2019-12-02-master-imports' 2019-12-02 22:05:35 -05:00
nds32 common: Move enable/disable_interrupts out of common.h 2019-12-02 18:25:01 -05:00
nios2 common: Move enable/disable_interrupts out of common.h 2019-12-02 18:25:01 -05:00
powerpc common: Move some board functions out of common.h 2019-12-02 18:25:21 -05:00
riscv riscv: add option to wait for ack from secondary harts in smp functions 2019-12-10 08:23:10 +08:00
sandbox common: Move command functions out of common.h 2019-12-02 18:25:02 -05:00
sh common: Move enable/disable_interrupts out of common.h 2019-12-02 18:25:01 -05:00
x86 x86: simplify ljmp to 32-bit code 2019-12-08 19:10:21 +08:00
xtensa common: Move interrupt functions into a new header 2019-12-02 18:25:00 -05:00
.gitignore
Kconfig sh: r2dplus: Enable OF control 2019-09-02 17:38:43 +02:00