mirror of
https://github.com/brain-hackers/u-boot-brain
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0ae7653128
Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn>
55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
#ifndef __GIC_H__
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#define __GIC_H__
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/* Register offsets for the ARM generic interrupt controller (GIC) */
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#define GIC_DIST_OFFSET 0x1000
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#define GIC_CPU_OFFSET_A9 0x0100
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#define GIC_CPU_OFFSET_A15 0x2000
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/* Distributor Registers */
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#define GICD_CTLR 0x0000
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#define GICD_TYPER 0x0004
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#define GICD_IIDR 0x0008
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#define GICD_STATUSR 0x0010
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#define GICD_SETSPI_NSR 0x0040
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#define GICD_CLRSPI_NSR 0x0048
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#define GICD_SETSPI_SR 0x0050
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#define GICD_CLRSPI_SR 0x0058
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#define GICD_SEIR 0x0068
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#define GICD_IGROUPRn 0x0080
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#define GICD_ISENABLERn 0x0100
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#define GICD_ICENABLERn 0x0180
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#define GICD_ISPENDRn 0x0200
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#define GICD_ICPENDRn 0x0280
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#define GICD_ISACTIVERn 0x0300
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#define GICD_ICACTIVERn 0x0380
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#define GICD_IPRIORITYRn 0x0400
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#define GICD_ITARGETSRn 0x0800
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#define GICD_ICFGR 0x0c00
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#define GICD_IGROUPMODRn 0x0d00
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#define GICD_NSACRn 0x0e00
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#define GICD_SGIR 0x0f00
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#define GICD_CPENDSGIRn 0x0f10
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#define GICD_SPENDSGIRn 0x0f20
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#define GICD_IROUTERn 0x6000
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/* Cpu Interface Memory Mapped Registers */
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#define GICC_CTLR 0x0000
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#define GICC_PMR 0x0004
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#define GICC_BPR 0x0008
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#define GICC_IAR 0x000C
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#define GICC_EOIR 0x0010
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#define GICC_RPR 0x0014
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#define GICC_HPPIR 0x0018
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#define GICC_ABPR 0x001c
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#define GICC_AIAR 0x0020
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#define GICC_AEOIR 0x0024
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#define GICC_AHPPIR 0x0028
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#define GICC_APRn 0x00d0
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#define GICC_NSAPRn 0x00e0
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#define GICC_IIDR 0x00fc
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#define GICC_DIR 0x1000
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#endif /* __GIC_H__ */
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