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https://github.com/brain-hackers/u-boot-brain
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0ae7653128
Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn>
165 lines
3.0 KiB
ArmAsm
165 lines
3.0 KiB
ArmAsm
/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <version.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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#include <asm/armv8/mmu.h>
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/*************************************************************************
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*
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* Startup Code (reset vector)
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*
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*************************************************************************/
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.globl _start
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_start:
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b reset
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.align 3
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.globl _TEXT_BASE
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_TEXT_BASE:
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.quad CONFIG_SYS_TEXT_BASE
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/*
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* These are defined in the linker script.
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*/
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.globl _end_ofs
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_end_ofs:
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.quad _end - _start
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.globl _bss_start_ofs
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_bss_start_ofs:
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.quad __bss_start - _start
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.globl _bss_end_ofs
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_bss_end_ofs:
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.quad __bss_end - _start
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reset:
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/*
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* Could be EL3/EL2/EL1, Initial State:
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* Little Endian, MMU Disabled, i/dCache Disabled
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*/
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adr x0, vectors
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switch_el x1, 3f, 2f, 1f
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3: msr vbar_el3, x0
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msr cptr_el3, xzr /* Enable FP/SIMD */
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ldr x0, =COUNTER_FREQUENCY
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msr cntfrq_el0, x0 /* Initialize CNTFRQ */
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b 0f
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2: msr vbar_el2, x0
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mov x0, #0x33ff
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msr cptr_el2, x0 /* Enable FP/SIMD */
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b 0f
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1: msr vbar_el1, x0
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mov x0, #3 << 20
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msr cpacr_el1, x0 /* Enable FP/SIMD */
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0:
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/* Cache/BPB/TLB Invalidate */
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bl __asm_flush_dcache_all /* dCache clean&invalidate */
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bl __asm_invalidate_icache_all /* iCache invalidate */
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bl __asm_invalidate_tlb_all /* invalidate TLBs */
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/* Processor specific initialization */
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bl lowlevel_init
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branch_if_master x0, x1, master_cpu
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/*
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* Slave CPUs
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*/
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slave_cpu:
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wfe
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ldr x1, =CPU_RELEASE_ADDR
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ldr x0, [x1]
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cbz x0, slave_cpu
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br x0 /* branch to the given address */
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/*
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* Master CPU
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*/
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master_cpu:
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bl _main
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/*-----------------------------------------------------------------------*/
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WEAK(lowlevel_init)
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/* Initialize GIC Secure Bank Status */
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mov x29, lr /* Save LR */
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bl gic_init
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branch_if_master x0, x1, 1f
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/*
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* Slave should wait for master clearing spin table.
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* This sync prevent salves observing incorrect
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* value of spin table and jumping to wrong place.
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*/
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bl wait_for_wakeup
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/*
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* All processors will enter EL2 and optionally EL1.
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*/
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bl armv8_switch_to_el2
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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bl armv8_switch_to_el1
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#endif
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1:
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mov lr, x29 /* Restore LR */
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ret
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ENDPROC(lowlevel_init)
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/*-----------------------------------------------------------------------*/
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ENTRY(c_runtime_cpu_setup)
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/* If I-cache is enabled invalidate it */
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#ifndef CONFIG_SYS_ICACHE_OFF
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ic iallu /* I+BTB cache invalidate */
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isb sy
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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/*
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* Setup MAIR and TCR.
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*/
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ldr x0, =MEMORY_ATTRIBUTES
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ldr x1, =TCR_FLAGS
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switch_el x2, 3f, 2f, 1f
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3: orr x1, x1, TCR_EL3_IPS_BITS
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msr mair_el3, x0
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msr tcr_el3, x1
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b 0f
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2: orr x1, x1, TCR_EL2_IPS_BITS
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msr mair_el2, x0
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msr tcr_el2, x1
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b 0f
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1: orr x1, x1, TCR_EL1_IPS_BITS
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msr mair_el1, x0
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msr tcr_el1, x1
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0:
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#endif
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/* Relocate vBAR */
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adr x0, vectors
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switch_el x1, 3f, 2f, 1f
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3: msr vbar_el3, x0
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b 0f
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2: msr vbar_el2, x0
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b 0f
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1: msr vbar_el1, x0
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0:
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ret
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ENDPROC(c_runtime_cpu_setup)
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