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https://github.com/brain-hackers/u-boot-brain
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23ad52ebb1
We want to be able to calculate the speed separately from actually setting the speed, so we can generate the required ACPI tables. Split out the calculation into its own function. Drop the double underscore on __dw_i2c_set_bus_speed while we are here. That is reserved for compiler internals. Signed-off-by: Simon Glass <sjg@chromium.org>
211 lines
5.4 KiB
C
211 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*/
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#ifndef __DW_I2C_H_
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#define __DW_I2C_H_
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#include <clk.h>
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#include <i2c.h>
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#include <reset.h>
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struct i2c_regs {
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u32 ic_con; /* 0x00 */
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u32 ic_tar; /* 0x04 */
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u32 ic_sar; /* 0x08 */
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u32 ic_hs_maddr; /* 0x0c */
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u32 ic_cmd_data; /* 0x10 */
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u32 ic_ss_scl_hcnt; /* 0x14 */
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u32 ic_ss_scl_lcnt; /* 0x18 */
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u32 ic_fs_scl_hcnt; /* 0x1c */
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u32 ic_fs_scl_lcnt; /* 0x20 */
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u32 ic_hs_scl_hcnt; /* 0x24 */
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u32 ic_hs_scl_lcnt; /* 0x28 */
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u32 ic_intr_stat; /* 0x2c */
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u32 ic_intr_mask; /* 0x30 */
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u32 ic_raw_intr_stat; /* 0x34 */
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u32 ic_rx_tl; /* 0x38 */
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u32 ic_tx_tl; /* 0x3c */
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u32 ic_clr_intr; /* 0x40 */
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u32 ic_clr_rx_under; /* 0x44 */
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u32 ic_clr_rx_over; /* 0x48 */
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u32 ic_clr_tx_over; /* 0x4c */
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u32 ic_clr_rd_req; /* 0x50 */
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u32 ic_clr_tx_abrt; /* 0x54 */
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u32 ic_clr_rx_done; /* 0x58 */
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u32 ic_clr_activity; /* 0x5c */
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u32 ic_clr_stop_det; /* 0x60 */
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u32 ic_clr_start_det; /* 0x64 */
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u32 ic_clr_gen_call; /* 0x68 */
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u32 ic_enable; /* 0x6c */
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u32 ic_status; /* 0x70 */
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u32 ic_txflr; /* 0x74 */
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u32 ic_rxflr; /* 0x78 */
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u32 ic_sda_hold; /* 0x7c */
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u32 ic_tx_abrt_source; /* 0x80 */
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u32 slv_data_nak_only;
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u32 dma_cr;
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u32 dma_tdlr;
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u32 dma_rdlr;
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u32 sda_setup;
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u32 ack_general_call;
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u32 ic_enable_status; /* 0x9c */
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u32 fs_spklen;
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u32 hs_spklen;
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u32 clr_restart_det;
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u8 reserved[0xf4 - 0xac];
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u32 comp_param1; /* 0xf4 */
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u32 comp_version;
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u32 comp_type;
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};
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#define IC_CLK 166666666
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#define NANO_TO_KILO 1000000
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/* High and low times in different speed modes (in ns) */
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#define MIN_SS_SCL_HIGHTIME 4000
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#define MIN_SS_SCL_LOWTIME 4700
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#define MIN_FS_SCL_HIGHTIME 600
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#define MIN_FS_SCL_LOWTIME 1300
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#define MIN_FP_SCL_HIGHTIME 260
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#define MIN_FP_SCL_LOWTIME 500
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#define MIN_HS_SCL_HIGHTIME 60
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#define MIN_HS_SCL_LOWTIME 160
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/* Worst case timeout for 1 byte is kept as 2ms */
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#define I2C_BYTE_TO (CONFIG_SYS_HZ/500)
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#define I2C_STOPDET_TO (CONFIG_SYS_HZ/500)
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#define I2C_BYTE_TO_BB (I2C_BYTE_TO * 16)
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/* i2c control register definitions */
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#define IC_CON_SD 0x0040
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#define IC_CON_RE 0x0020
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#define IC_CON_10BITADDRMASTER 0x0010
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#define IC_CON_10BITADDR_SLAVE 0x0008
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#define IC_CON_SPD_MSK 0x0006
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#define IC_CON_SPD_SS 0x0002
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#define IC_CON_SPD_FS 0x0004
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#define IC_CON_SPD_HS 0x0006
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#define IC_CON_MM 0x0001
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/* i2c target address register definitions */
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#define TAR_ADDR 0x0050
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/* i2c slave address register definitions */
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#define IC_SLAVE_ADDR 0x0002
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/* i2c data buffer and command register definitions */
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#define IC_CMD 0x0100
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#define IC_STOP 0x0200
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/* i2c interrupt status register definitions */
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#define IC_GEN_CALL 0x0800
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#define IC_START_DET 0x0400
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#define IC_STOP_DET 0x0200
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#define IC_ACTIVITY 0x0100
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#define IC_RX_DONE 0x0080
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#define IC_TX_ABRT 0x0040
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#define IC_RD_REQ 0x0020
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#define IC_TX_EMPTY 0x0010
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#define IC_TX_OVER 0x0008
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#define IC_RX_FULL 0x0004
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#define IC_RX_OVER 0x0002
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#define IC_RX_UNDER 0x0001
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/* fifo threshold register definitions */
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#define IC_TL0 0x00
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#define IC_TL1 0x01
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#define IC_TL2 0x02
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#define IC_TL3 0x03
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#define IC_TL4 0x04
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#define IC_TL5 0x05
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#define IC_TL6 0x06
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#define IC_TL7 0x07
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#define IC_RX_TL IC_TL0
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#define IC_TX_TL IC_TL0
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/* i2c enable register definitions */
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#define IC_ENABLE_0B 0x0001
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/* i2c status register definitions */
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#define IC_STATUS_SA 0x0040
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#define IC_STATUS_MA 0x0020
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#define IC_STATUS_RFF 0x0010
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#define IC_STATUS_RFNE 0x0008
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#define IC_STATUS_TFE 0x0004
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#define IC_STATUS_TFNF 0x0002
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#define IC_STATUS_ACT 0x0001
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/**
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* struct dw_scl_sda_cfg - I2C timing configuration
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*
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* @has_high_speed: Support high speed (3.4Mbps)
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* @ss_hcnt: Standard speed high time in ns
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* @fs_hcnt: Fast speed high time in ns
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* @ss_lcnt: Standard speed low time in ns
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* @fs_lcnt: Fast speed low time in ns
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* @sda_hold: SDA hold time
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*/
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struct dw_scl_sda_cfg {
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bool has_high_speed;
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u32 ss_hcnt;
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u32 fs_hcnt;
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u32 ss_lcnt;
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u32 fs_lcnt;
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u32 sda_hold;
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};
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/**
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* struct dw_i2c_speed_config - timings to use for a particular speed
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*
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* This holds calculated values to be written to the I2C controller. Each value
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* is represented as a number of IC clock cycles.
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*
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* @scl_lcnt: Low count value for SCL
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* @scl_hcnt: High count value for SCL
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* @sda_hold: Data hold count
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* @speed_mode: Speed mode being used
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*/
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struct dw_i2c_speed_config {
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/* SCL high and low period count */
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u16 scl_lcnt;
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u16 scl_hcnt;
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u32 sda_hold;
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enum i2c_speed_mode speed_mode;
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};
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/**
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* struct dw_i2c - private information for the bus
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*
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* @regs: Registers pointer
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* @scl_sda_cfg: Deprecated information for x86 (should move to device tree)
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* @resets: Resets for the I2C controller
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* @scl_rise_time_ns: Configured SCL rise time in nanoseconds
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* @scl_fall_time_ns: Configured SCL fall time in nanoseconds
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* @sda_hold_time_ns: Configured SDA hold time in nanoseconds
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* @has_spk_cnt: true if the spike-count register is present
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* @clk: Clock input to the I2C controller
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*/
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struct dw_i2c {
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struct i2c_regs *regs;
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struct dw_scl_sda_cfg *scl_sda_cfg;
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struct reset_ctl_bulk resets;
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u32 scl_rise_time_ns;
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u32 scl_fall_time_ns;
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u32 sda_hold_time_ns;
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bool has_spk_cnt;
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#if CONFIG_IS_ENABLED(CLK)
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struct clk clk;
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#endif
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};
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extern const struct dm_i2c_ops designware_i2c_ops;
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int designware_i2c_probe(struct udevice *bus);
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int designware_i2c_remove(struct udevice *dev);
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int designware_i2c_ofdata_to_platdata(struct udevice *bus);
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#endif /* __DW_I2C_H_ */
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