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https://github.com/brain-hackers/u-boot-brain
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![Stephen Warren](/assets/img/avatar_default.png)
The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
188 lines
4.7 KiB
C
188 lines
4.7 KiB
C
/*
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* Qualcomm SDHCI driver - SD/eMMC controller
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*
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* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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*
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* Based on Linux driver
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <sdhci.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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/* Non-standard registers needed for SDHCI startup */
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#define SDCC_MCI_POWER 0x0
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#define SDCC_MCI_POWER_SW_RST BIT(7)
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/* This is undocumented register */
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#define SDCC_MCI_VERSION 0x50
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#define SDCC_MCI_VERSION_MAJOR_SHIFT 28
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#define SDCC_MCI_VERSION_MAJOR_MASK (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT)
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#define SDCC_MCI_VERSION_MINOR_MASK 0xff
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#define SDCC_MCI_STATUS2 0x6C
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#define SDCC_MCI_STATUS2_MCI_ACT 0x1
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#define SDCC_MCI_HC_MODE 0x78
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/* Offset to SDHCI registers */
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#define SDCC_SDHCI_OFFSET 0x900
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/* Non standard (?) SDHCI register */
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#define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c
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struct msm_sdhc {
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struct sdhci_host host;
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void *base;
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};
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DECLARE_GLOBAL_DATA_PTR;
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static int msm_sdc_clk_init(struct udevice *dev)
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{
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uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
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"clock-frequency", 400000);
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uint clkd[2]; /* clk_id and clk_no */
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int clk_offset;
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struct udevice *clk_dev;
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struct clk clk;
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int ret;
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ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd,
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2);
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if (ret)
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return ret;
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clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
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if (clk_offset < 0)
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return clk_offset;
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ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
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if (ret)
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return ret;
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clk.id = clkd[1];
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ret = clk_request(clk_dev, &clk);
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if (ret < 0)
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return ret;
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ret = clk_set_rate(&clk, clk_rate);
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clk_free(&clk);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int msm_sdc_probe(struct udevice *dev)
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{
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struct msm_sdhc *prv = dev_get_priv(dev);
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struct sdhci_host *host = &prv->host;
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u32 core_version, core_minor, core_major;
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int ret;
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host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
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/* Init clocks */
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ret = msm_sdc_clk_init(dev);
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if (ret)
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return ret;
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/* Reset the core and Enable SDHC mode */
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writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST,
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prv->base + SDCC_MCI_POWER);
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/* Wait for reset to be written to register */
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if (wait_for_bit(__func__, prv->base + SDCC_MCI_STATUS2,
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SDCC_MCI_STATUS2_MCI_ACT, false, 10, false)) {
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printf("msm_sdhci: reset request failed\n");
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return -EIO;
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}
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/* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
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if (wait_for_bit(__func__, prv->base + SDCC_MCI_POWER,
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SDCC_MCI_POWER_SW_RST, false, 2, false)) {
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printf("msm_sdhci: stuck in reset\n");
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return -ETIMEDOUT;
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}
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/* Enable host-controller mode */
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writel(1, prv->base + SDCC_MCI_HC_MODE);
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core_version = readl(prv->base + SDCC_MCI_VERSION);
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core_major = (core_version & SDCC_MCI_VERSION_MAJOR_MASK);
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core_major >>= SDCC_MCI_VERSION_MAJOR_SHIFT;
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core_minor = core_version & SDCC_MCI_VERSION_MINOR_MASK;
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/*
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* Support for some capabilities is not advertised by newer
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* controller versions and must be explicitly enabled.
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*/
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if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
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u32 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
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caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
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writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0);
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}
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/* Set host controller version */
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host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
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/* automatically detect max and min speed */
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return add_sdhci(host, 0, 0);
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}
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static int msm_sdc_remove(struct udevice *dev)
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{
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struct msm_sdhc *priv = dev_get_priv(dev);
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/* Disable host-controller mode */
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writel(0, priv->base + SDCC_MCI_HC_MODE);
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return 0;
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}
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static int msm_ofdata_to_platdata(struct udevice *dev)
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{
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struct udevice *parent = dev->parent;
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struct msm_sdhc *priv = dev_get_priv(dev);
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struct sdhci_host *host = &priv->host;
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host->name = strdup(dev->name);
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host->ioaddr = (void *)dev_get_addr(dev);
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host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
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"bus-width", 4);
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host->index = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, "index", 0);
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priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
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parent->of_offset,
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dev->of_offset,
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"reg", 1, NULL);
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if (priv->base == (void *)FDT_ADDR_T_NONE ||
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host->ioaddr == (void *)FDT_ADDR_T_NONE)
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return -EINVAL;
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return 0;
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}
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static const struct udevice_id msm_mmc_ids[] = {
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{ .compatible = "qcom,sdhci-msm-v4" },
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{ }
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};
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U_BOOT_DRIVER(msm_sdc_drv) = {
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.name = "msm_sdc",
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.id = UCLASS_MMC,
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.of_match = msm_mmc_ids,
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.ofdata_to_platdata = msm_ofdata_to_platdata,
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.probe = msm_sdc_probe,
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.remove = msm_sdc_remove,
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.priv_auto_alloc_size = sizeof(struct msm_sdhc),
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};
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