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https://github.com/brain-hackers/u-boot-brain
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![Prabhakar Kushwaha](/assets/img/avatar_default.png)
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
75 lines
1.5 KiB
C
75 lines
1.5 KiB
C
/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/immap_lsch2.h>
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struct serdes_config {
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u32 protocol;
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u8 lanes[SRDS_MAX_LANES];
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};
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static struct serdes_config serdes1_cfg_tbl[] = {
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{0x2208, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, SATA1} },
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{0x0008, {NONE, NONE, NONE, SATA1} },
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{0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} },
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{0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
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{0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} },
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{0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
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{0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
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{0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
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{0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
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{}
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};
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static struct serdes_config *serdes_cfg_tbl[] = {
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serdes1_cfg_tbl,
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};
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
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{
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struct serdes_config *ptr;
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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ptr = serdes_cfg_tbl[serdes];
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while (ptr->protocol) {
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if (ptr->protocol == cfg)
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return ptr->lanes[lane];
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ptr++;
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}
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return 0;
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}
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int is_serdes_prtcl_valid(int serdes, u32 prtcl)
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{
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int i;
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struct serdes_config *ptr;
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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ptr = serdes_cfg_tbl[serdes];
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while (ptr->protocol) {
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if (ptr->protocol == prtcl)
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break;
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ptr++;
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}
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if (!ptr->protocol)
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return 0;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (ptr->lanes[i] != NONE)
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return 1;
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}
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return 0;
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}
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