mirror of
https://github.com/brain-hackers/u-boot-brain
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ca4abdcdfa
As suggested by Vikas Manocha, update embedded SRAM address to use AXI SRAM available on D1 domain instead of using AHB SRAM (D2 domain). On some STM32H743 SoCs, D2 domain SRAM is accessible even if SRAMxEN bit in AHB2ENR bits are not set whereas on others SoCs version it's not accessible. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
52 lines
1.2 KiB
C
52 lines
1.2 KiB
C
/*
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* Copyright (C) STMicroelectronics SA 2017
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* Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <config.h>
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#define CONFIG_SYS_FLASH_BASE 0x08000000
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#define CONFIG_SYS_INIT_SP_ADDR 0x24040000
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#define CONFIG_SYS_TEXT_BASE 0x08000000
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/*
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* Configuration of the external SDRAM memory
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_RAM_BASE 0xD0000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
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#define CONFIG_SYS_LOAD_ADDR 0xD0400000
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#define CONFIG_LOADADDR 0xD0400000
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#define CONFIG_ENV_SIZE (8 << 10)
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#define CONFIG_SYS_ARCH_TIMER
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#define CONFIG_SYS_HZ_CLOCK 250000000
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
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#define CONFIG_BOOTARGS \
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"console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
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/*
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* Command line configuration.
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*/
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_CMD_CACHE
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#define CONFIG_BOARD_LATE_INIT
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#endif /* __CONFIG_H */
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