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https://github.com/brain-hackers/u-boot-brain
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cbeedafdc8
This patch adds USB configs to support the USB OTG port(consist of DWC2 controller) and the USB Host port(consist of EHCI and OHCI controllers) on evb-rv1108 board, and also support fastboot over USB and USB mass storage. Signed-off-by: William Wu <william.wu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
35 lines
1008 B
C
35 lines
1008 B
C
/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_RV1108_COMMON_H
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#define __CONFIG_RV1108_COMMON_H
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#include <asm/arch/hardware.h>
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#include "rockchip-common.h"
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_SYS_MALLOC_LEN (32 << 20)
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
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/* TIMER1,initialized by ddr initialize code */
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#define CONFIG_SYS_TIMER_BASE 0x10350020
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#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_SYS_SDRAM_BASE 0x60000000
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_TEXT_BASE CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000)
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/* rockchip ohci host driver */
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
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#endif
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