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https://github.com/brain-hackers/u-boot-brain
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0a9bb489bf
Since Intel ICH SPI driver has been converted to driver model, we need add an alias for SPI node in the board dts files otherwise SPI flash won't be detected due to 'invalid bus' error. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
141 lines
2.8 KiB
Plaintext
141 lines
2.8 KiB
Plaintext
/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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/include/ "skeleton.dtsi"
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/include/ "serial.dtsi"
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/ {
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model = "Intel Crown Bay";
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compatible = "intel,crownbay", "intel,queensbay";
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aliases {
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spi0 = "/spi";
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};
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config {
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silent_console = <0>;
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};
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gpioa {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0 0x20>;
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bank-name = "A";
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};
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gpiob {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x20 0x20>;
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bank-name = "B";
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};
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chosen {
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/*
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* By default the legacy superio serial port is used as the
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* U-Boot serial console. If we want to use UART from Topcliff
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* PCH as the console, change this property to &pciuart#.
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*
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* For example, stdout-path = &pciuart0 will use the first
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* UART on Topcliff PCH.
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*/
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stdout-path = "/serial";
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};
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ich-spi";
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spi-flash@0 {
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reg = <0>;
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compatible = "sst,25vf016b", "spi-flash";
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memory-map = <0xffe00000 0x00200000>;
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};
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};
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microcode {
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update@0 {
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#include "microcode/m0220661105_cv.dtsi"
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};
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};
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pci {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "intel,pci";
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device_type = "pci";
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pcie@17,0 {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "intel,pci";
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device_type = "pci";
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topcliff@0,0 {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "intel,pci";
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device_type = "pci";
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pciuart0: uart@a,1 {
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compatible = "pci8086,8811.00",
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"pci8086,8811",
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"pciclass,070002",
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"pciclass,0700",
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"x86-uart";
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reg = <0x00025100 0x0 0x0 0x0 0x0
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0x01025110 0x0 0x0 0x0 0x0>;
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reg-shift = <0>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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};
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pciuart1: uart@a,2 {
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compatible = "pci8086,8812.00",
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"pci8086,8812",
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"pciclass,070002",
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"pciclass,0700",
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"x86-uart";
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reg = <0x00025200 0x0 0x0 0x0 0x0
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0x01025210 0x0 0x0 0x0 0x0>;
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reg-shift = <0>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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};
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pciuart2: uart@a,3 {
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compatible = "pci8086,8813.00",
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"pci8086,8813",
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"pciclass,070002",
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"pciclass,0700",
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"x86-uart";
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reg = <0x00025300 0x0 0x0 0x0 0x0
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0x01025310 0x0 0x0 0x0 0x0>;
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reg-shift = <0>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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};
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pciuart3: uart@a,4 {
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compatible = "pci8086,8814.00",
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"pci8086,8814",
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"pciclass,070002",
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"pciclass,0700",
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"x86-uart";
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reg = <0x00025400 0x0 0x0 0x0 0x0
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0x01025410 0x0 0x0 0x0 0x0>;
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reg-shift = <0>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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};
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};
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};
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};
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};
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