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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-18 16:08:53 +09:00
![Stephen Warren](/assets/img/avatar_default.png)
Tegra124's MMC controller is very similar to earlier SoC generations, and can be supported by the same driver. However, there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW. This patch updates the driver to support that new compatible value. That said, the HW differences are only relevant when enabling certain high-performance transfer modes. Since the driver is currently very simple and doesn't enable those modes, we don't actually need to address any of these HW differences in the code yet, hence the simple nature of this patch. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
698 lines
18 KiB
C
698 lines
18 KiB
C
/*
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* (C) Copyright 2009 SAMSUNG Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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* Jaehoon Chung <jh80.chung@samsung.com>
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* Portions Copyright 2011-2013 NVIDIA Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <bouncebuf.h>
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/tegra_mmc.h>
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#include <mmc.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct mmc mmc_dev[MAX_HOSTS];
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struct mmc_host mmc_host[MAX_HOSTS];
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#ifndef CONFIG_OF_CONTROL
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#error "Please enable device tree support to use this driver"
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#endif
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static void mmc_set_power(struct mmc_host *host, unsigned short power)
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{
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u8 pwr = 0;
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debug("%s: power = %x\n", __func__, power);
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if (power != (unsigned short)-1) {
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switch (1 << power) {
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case MMC_VDD_165_195:
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pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
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break;
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case MMC_VDD_29_30:
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case MMC_VDD_30_31:
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pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
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break;
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case MMC_VDD_32_33:
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case MMC_VDD_33_34:
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pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
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break;
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}
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}
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debug("%s: pwr = %X\n", __func__, pwr);
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/* Set the bus voltage first (if any) */
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writeb(pwr, &host->reg->pwrcon);
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if (pwr == 0)
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return;
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/* Now enable bus power */
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pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
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writeb(pwr, &host->reg->pwrcon);
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}
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static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data,
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struct bounce_buffer *bbstate)
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{
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unsigned char ctrl;
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debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
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bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
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data->blocksize);
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writel((u32)bbstate->bounce_buffer, &host->reg->sysad);
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/*
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* DMASEL[4:3]
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* 00 = Selects SDMA
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* 01 = Reserved
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* 10 = Selects 32-bit Address ADMA2
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* 11 = Selects 64-bit Address ADMA2
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*/
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ctrl = readb(&host->reg->hostctl);
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ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
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ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
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writeb(ctrl, &host->reg->hostctl);
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/* We do not handle DMA boundaries, so set it to max (512 KiB) */
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writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
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writew(data->blocks, &host->reg->blkcnt);
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}
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static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
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{
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unsigned short mode;
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debug(" mmc_set_transfer_mode called\n");
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/*
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* TRNMOD
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* MUL1SIN0[5] : Multi/Single Block Select
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* RD1WT0[4] : Data Transfer Direction Select
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* 1 = read
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* 0 = write
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* ENACMD12[2] : Auto CMD12 Enable
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* ENBLKCNT[1] : Block Count Enable
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* ENDMA[0] : DMA Enable
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*/
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mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
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TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
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if (data->blocks > 1)
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mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
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if (data->flags & MMC_DATA_READ)
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mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
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writew(mode, &host->reg->trnmod);
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}
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static int mmc_wait_inhibit(struct mmc_host *host,
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struct mmc_cmd *cmd,
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struct mmc_data *data,
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unsigned int timeout)
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{
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/*
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* PRNSTS
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* CMDINHDAT[1] : Command Inhibit (DAT)
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* CMDINHCMD[0] : Command Inhibit (CMD)
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*/
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unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
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/*
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* We shouldn't wait for data inhibit for stop commands, even
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* though they might use busy signaling
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*/
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if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
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mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
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while (readl(&host->reg->prnsts) & mask) {
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if (timeout == 0) {
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printf("%s: timeout error\n", __func__);
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return -1;
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}
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timeout--;
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udelay(1000);
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}
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return 0;
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}
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static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data, struct bounce_buffer *bbstate)
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{
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struct mmc_host *host = (struct mmc_host *)mmc->priv;
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int flags, i;
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int result;
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unsigned int mask = 0;
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unsigned int retry = 0x100000;
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debug(" mmc_send_cmd called\n");
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result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
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if (result < 0)
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return result;
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if (data)
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mmc_prepare_data(host, data, bbstate);
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debug("cmd->arg: %08x\n", cmd->cmdarg);
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writel(cmd->cmdarg, &host->reg->argument);
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if (data)
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mmc_set_transfer_mode(host, data);
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if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
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return -1;
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/*
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* CMDREG
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* CMDIDX[13:8] : Command index
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* DATAPRNT[5] : Data Present Select
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* ENCMDIDX[4] : Command Index Check Enable
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* ENCMDCRC[3] : Command CRC Check Enable
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* RSPTYP[1:0]
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* 00 = No Response
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* 01 = Length 136
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* 10 = Length 48
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* 11 = Length 48 Check busy after response
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*/
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if (!(cmd->resp_type & MMC_RSP_PRESENT))
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flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
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else if (cmd->resp_type & MMC_RSP_136)
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flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
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else if (cmd->resp_type & MMC_RSP_BUSY)
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flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
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else
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flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
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if (cmd->resp_type & MMC_RSP_CRC)
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flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
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if (cmd->resp_type & MMC_RSP_OPCODE)
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flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
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if (data)
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flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
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debug("cmd: %d\n", cmd->cmdidx);
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writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
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for (i = 0; i < retry; i++) {
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mask = readl(&host->reg->norintsts);
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/* Command Complete */
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if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
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if (!data)
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writel(mask, &host->reg->norintsts);
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break;
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}
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}
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if (i == retry) {
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printf("%s: waiting for status update\n", __func__);
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writel(mask, &host->reg->norintsts);
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return TIMEOUT;
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}
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if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
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/* Timeout Error */
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debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
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writel(mask, &host->reg->norintsts);
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return TIMEOUT;
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} else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
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/* Error Interrupt */
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debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
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writel(mask, &host->reg->norintsts);
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return -1;
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}
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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if (cmd->resp_type & MMC_RSP_136) {
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/* CRC is stripped so we need to do some shifting. */
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for (i = 0; i < 4; i++) {
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unsigned int offset =
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(unsigned int)(&host->reg->rspreg3 - i);
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cmd->response[i] = readl(offset) << 8;
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if (i != 3) {
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cmd->response[i] |=
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readb(offset - 1);
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}
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debug("cmd->resp[%d]: %08x\n",
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i, cmd->response[i]);
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}
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} else if (cmd->resp_type & MMC_RSP_BUSY) {
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for (i = 0; i < retry; i++) {
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/* PRNTDATA[23:20] : DAT[3:0] Line Signal */
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if (readl(&host->reg->prnsts)
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& (1 << 20)) /* DAT[0] */
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break;
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}
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if (i == retry) {
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printf("%s: card is still busy\n", __func__);
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writel(mask, &host->reg->norintsts);
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return TIMEOUT;
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}
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cmd->response[0] = readl(&host->reg->rspreg0);
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debug("cmd->resp[0]: %08x\n", cmd->response[0]);
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} else {
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cmd->response[0] = readl(&host->reg->rspreg0);
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debug("cmd->resp[0]: %08x\n", cmd->response[0]);
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}
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}
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if (data) {
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unsigned long start = get_timer(0);
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while (1) {
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mask = readl(&host->reg->norintsts);
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if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
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/* Error Interrupt */
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writel(mask, &host->reg->norintsts);
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printf("%s: error during transfer: 0x%08x\n",
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__func__, mask);
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return -1;
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} else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
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/*
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* DMA Interrupt, restart the transfer where
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* it was interrupted.
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*/
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unsigned int address = readl(&host->reg->sysad);
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debug("DMA end\n");
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writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
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&host->reg->norintsts);
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writel(address, &host->reg->sysad);
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} else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
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/* Transfer Complete */
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debug("r/w is done\n");
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break;
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} else if (get_timer(start) > 2000UL) {
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writel(mask, &host->reg->norintsts);
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printf("%s: MMC Timeout\n"
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" Interrupt status 0x%08x\n"
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" Interrupt status enable 0x%08x\n"
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" Interrupt signal enable 0x%08x\n"
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" Present status 0x%08x\n",
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__func__, mask,
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readl(&host->reg->norintstsen),
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readl(&host->reg->norintsigen),
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readl(&host->reg->prnsts));
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return -1;
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}
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}
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writel(mask, &host->reg->norintsts);
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}
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udelay(1000);
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return 0;
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}
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static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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void *buf;
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unsigned int bbflags;
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size_t len;
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struct bounce_buffer bbstate;
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int ret;
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if (data) {
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if (data->flags & MMC_DATA_READ) {
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buf = data->dest;
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bbflags = GEN_BB_WRITE;
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} else {
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buf = (void *)data->src;
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bbflags = GEN_BB_READ;
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}
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len = data->blocks * data->blocksize;
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bounce_buffer_start(&bbstate, buf, len, bbflags);
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}
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ret = mmc_send_cmd_bounced(mmc, cmd, data, &bbstate);
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if (data)
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bounce_buffer_stop(&bbstate);
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return ret;
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}
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static void mmc_change_clock(struct mmc_host *host, uint clock)
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{
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int div;
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unsigned short clk;
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unsigned long timeout;
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debug(" mmc_change_clock called\n");
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/*
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* Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
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*/
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if (clock == 0)
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goto out;
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clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
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&div);
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debug("div = %d\n", div);
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writew(0, &host->reg->clkcon);
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/*
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* CLKCON
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* SELFREQ[15:8] : base clock divided by value
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* ENSDCLK[2] : SD Clock Enable
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* STBLINTCLK[1] : Internal Clock Stable
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* ENINTCLK[0] : Internal Clock Enable
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*/
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div >>= 1;
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clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
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TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
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writew(clk, &host->reg->clkcon);
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/* Wait max 10 ms */
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timeout = 10;
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while (!(readw(&host->reg->clkcon) &
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TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
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if (timeout == 0) {
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printf("%s: timeout error\n", __func__);
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return;
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}
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timeout--;
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udelay(1000);
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}
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clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
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writew(clk, &host->reg->clkcon);
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debug("mmc_change_clock: clkcon = %08X\n", clk);
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out:
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host->clock = clock;
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}
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static void mmc_set_ios(struct mmc *mmc)
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{
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struct mmc_host *host = mmc->priv;
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unsigned char ctrl;
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debug(" mmc_set_ios called\n");
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debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
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/* Change clock first */
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mmc_change_clock(host, mmc->clock);
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ctrl = readb(&host->reg->hostctl);
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/*
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* WIDE8[5]
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* 0 = Depend on WIDE4
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* 1 = 8-bit mode
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* WIDE4[1]
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* 1 = 4-bit mode
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* 0 = 1-bit mode
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*/
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if (mmc->bus_width == 8)
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ctrl |= (1 << 5);
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else if (mmc->bus_width == 4)
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ctrl |= (1 << 1);
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else
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ctrl &= ~(1 << 1);
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writeb(ctrl, &host->reg->hostctl);
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debug("mmc_set_ios: hostctl = %08X\n", ctrl);
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}
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static void mmc_reset(struct mmc_host *host, struct mmc *mmc)
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{
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unsigned int timeout;
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debug(" mmc_reset called\n");
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/*
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* RSTALL[0] : Software reset for all
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* 1 = reset
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* 0 = work
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*/
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writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
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host->clock = 0;
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/* Wait max 100 ms */
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timeout = 100;
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/* hw clears the bit when it's done */
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while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
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if (timeout == 0) {
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printf("%s: timeout error\n", __func__);
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return;
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}
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timeout--;
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udelay(1000);
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}
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/* Set SD bus voltage & enable bus power */
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mmc_set_power(host, fls(mmc->voltages) - 1);
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debug("%s: power control = %02X, host control = %02X\n", __func__,
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readb(&host->reg->pwrcon), readb(&host->reg->hostctl));
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/* Make sure SDIO pads are set up */
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pad_init_mmc(host);
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}
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static int mmc_core_init(struct mmc *mmc)
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{
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struct mmc_host *host = (struct mmc_host *)mmc->priv;
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unsigned int mask;
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debug(" mmc_core_init called\n");
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mmc_reset(host, mmc);
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host->version = readw(&host->reg->hcver);
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debug("host version = %x\n", host->version);
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/* mask all */
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writel(0xffffffff, &host->reg->norintstsen);
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writel(0xffffffff, &host->reg->norintsigen);
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writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */
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/*
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* NORMAL Interrupt Status Enable Register init
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* [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
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* [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
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* [3] ENSTADMAINT : DMA boundary interrupt
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* [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
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* [0] ENSTACMDCMPLT : Command Complete Status Enable
|
|
*/
|
|
mask = readl(&host->reg->norintstsen);
|
|
mask &= ~(0xffff);
|
|
mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
|
|
TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
|
|
TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
|
|
TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
|
|
TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
|
|
writel(mask, &host->reg->norintstsen);
|
|
|
|
/*
|
|
* NORMAL Interrupt Signal Enable Register init
|
|
* [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
|
|
*/
|
|
mask = readl(&host->reg->norintsigen);
|
|
mask &= ~(0xffff);
|
|
mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
|
|
writel(mask, &host->reg->norintsigen);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int tegra_mmc_getcd(struct mmc *mmc)
|
|
{
|
|
struct mmc_host *host = (struct mmc_host *)mmc->priv;
|
|
|
|
debug("tegra_mmc_getcd called\n");
|
|
|
|
if (fdt_gpio_isvalid(&host->cd_gpio))
|
|
return fdtdec_get_gpio(&host->cd_gpio);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int do_mmc_init(int dev_index)
|
|
{
|
|
struct mmc_host *host;
|
|
char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
|
|
struct mmc *mmc;
|
|
|
|
/* DT should have been read & host config filled in */
|
|
host = &mmc_host[dev_index];
|
|
if (!host->enabled)
|
|
return -1;
|
|
|
|
debug(" do_mmc_init: index %d, bus width %d "
|
|
"pwr_gpio %d cd_gpio %d\n",
|
|
dev_index, host->width,
|
|
host->pwr_gpio.gpio, host->cd_gpio.gpio);
|
|
|
|
host->clock = 0;
|
|
clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
|
|
|
|
if (fdt_gpio_isvalid(&host->pwr_gpio)) {
|
|
sprintf(gpusage, "SD/MMC%d PWR", dev_index);
|
|
gpio_request(host->pwr_gpio.gpio, gpusage);
|
|
gpio_direction_output(host->pwr_gpio.gpio, 1);
|
|
debug(" Power GPIO name = %s\n", host->pwr_gpio.name);
|
|
}
|
|
|
|
if (fdt_gpio_isvalid(&host->cd_gpio)) {
|
|
sprintf(gpusage, "SD/MMC%d CD", dev_index);
|
|
gpio_request(host->cd_gpio.gpio, gpusage);
|
|
gpio_direction_input(host->cd_gpio.gpio);
|
|
debug(" CD GPIO name = %s\n", host->cd_gpio.name);
|
|
}
|
|
|
|
mmc = &mmc_dev[dev_index];
|
|
|
|
sprintf(mmc->name, "Tegra SD/MMC");
|
|
mmc->priv = host;
|
|
mmc->send_cmd = mmc_send_cmd;
|
|
mmc->set_ios = mmc_set_ios;
|
|
mmc->init = mmc_core_init;
|
|
mmc->getcd = tegra_mmc_getcd;
|
|
mmc->getwp = NULL;
|
|
|
|
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
|
|
mmc->host_caps = 0;
|
|
if (host->width == 8)
|
|
mmc->host_caps |= MMC_MODE_8BIT;
|
|
if (host->width >= 4)
|
|
mmc->host_caps |= MMC_MODE_4BIT;
|
|
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
|
|
|
|
/*
|
|
* min freq is for card identification, and is the highest
|
|
* low-speed SDIO card frequency (actually 400KHz)
|
|
* max freq is highest HS eMMC clock as per the SD/MMC spec
|
|
* (actually 52MHz)
|
|
*/
|
|
mmc->f_min = 375000;
|
|
mmc->f_max = 48000000;
|
|
|
|
mmc_register(mmc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Get the host address and peripheral ID for a node.
|
|
*
|
|
* @param blob fdt blob
|
|
* @param node Device index (0-3)
|
|
* @param host Structure to fill in (reg, width, mmc_id)
|
|
*/
|
|
static int mmc_get_config(const void *blob, int node, struct mmc_host *host)
|
|
{
|
|
debug("%s: node = %d\n", __func__, node);
|
|
|
|
host->enabled = fdtdec_get_is_enabled(blob, node);
|
|
|
|
host->reg = (struct tegra_mmc *)fdtdec_get_addr(blob, node, "reg");
|
|
if ((fdt_addr_t)host->reg == FDT_ADDR_T_NONE) {
|
|
debug("%s: no sdmmc base reg info found\n", __func__);
|
|
return -FDT_ERR_NOTFOUND;
|
|
}
|
|
|
|
host->mmc_id = clock_decode_periph_id(blob, node);
|
|
if (host->mmc_id == PERIPH_ID_NONE) {
|
|
debug("%s: could not decode periph id\n", __func__);
|
|
return -FDT_ERR_NOTFOUND;
|
|
}
|
|
|
|
/*
|
|
* NOTE: mmc->bus_width is determined by mmc.c dynamically.
|
|
* TBD: Override it with this value?
|
|
*/
|
|
host->width = fdtdec_get_int(blob, node, "bus-width", 0);
|
|
if (!host->width)
|
|
debug("%s: no sdmmc width found\n", __func__);
|
|
|
|
/* These GPIOs are optional */
|
|
fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio);
|
|
fdtdec_decode_gpio(blob, node, "wp-gpios", &host->wp_gpio);
|
|
fdtdec_decode_gpio(blob, node, "power-gpios", &host->pwr_gpio);
|
|
|
|
debug("%s: found controller at %p, width = %d, periph_id = %d\n",
|
|
__func__, host->reg, host->width, host->mmc_id);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Process a list of nodes, adding them to our list of SDMMC ports.
|
|
*
|
|
* @param blob fdt blob
|
|
* @param node_list list of nodes to process (any <=0 are ignored)
|
|
* @param count number of nodes to process
|
|
* @return 0 if ok, -1 on error
|
|
*/
|
|
static int process_nodes(const void *blob, int node_list[], int count)
|
|
{
|
|
struct mmc_host *host;
|
|
int i, node;
|
|
|
|
debug("%s: count = %d\n", __func__, count);
|
|
|
|
/* build mmc_host[] for each controller */
|
|
for (i = 0; i < count; i++) {
|
|
node = node_list[i];
|
|
if (node <= 0)
|
|
continue;
|
|
|
|
host = &mmc_host[i];
|
|
host->id = i;
|
|
|
|
if (mmc_get_config(blob, node, host)) {
|
|
printf("%s: failed to decode dev %d\n", __func__, i);
|
|
return -1;
|
|
}
|
|
do_mmc_init(i);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void tegra_mmc_init(void)
|
|
{
|
|
int node_list[MAX_HOSTS], count;
|
|
const void *blob = gd->fdt_blob;
|
|
debug("%s entry\n", __func__);
|
|
|
|
/* See if any Tegra124 MMC controllers are present */
|
|
count = fdtdec_find_aliases_for_id(blob, "sdhci",
|
|
COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, MAX_HOSTS);
|
|
debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count);
|
|
if (process_nodes(blob, node_list, count)) {
|
|
printf("%s: Error processing T30 mmc node(s)!\n", __func__);
|
|
return;
|
|
}
|
|
|
|
/* See if any Tegra30 MMC controllers are present */
|
|
count = fdtdec_find_aliases_for_id(blob, "sdhci",
|
|
COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS);
|
|
debug("%s: count of T30 sdhci nodes is %d\n", __func__, count);
|
|
if (process_nodes(blob, node_list, count)) {
|
|
printf("%s: Error processing T30 mmc node(s)!\n", __func__);
|
|
return;
|
|
}
|
|
|
|
/* Now look for any Tegra20 MMC controllers */
|
|
count = fdtdec_find_aliases_for_id(blob, "sdhci",
|
|
COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, MAX_HOSTS);
|
|
debug("%s: count of T20 sdhci nodes is %d\n", __func__, count);
|
|
if (process_nodes(blob, node_list, count)) {
|
|
printf("%s: Error processing T20 mmc node(s)!\n", __func__);
|
|
return;
|
|
}
|
|
}
|