mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-09 06:13:21 +09:00
![Scott Wood](/assets/img/avatar_default.png)
Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL and CONFIG_SPL_BUILD, respectively. CONFIG_NAND_SPL can be removed once the last mpc85xx nand_spl target is gone. CONFIG_RAMBOOT will need to remain for other use cases, but it doesn't seem right to overload it for meaning SPL as well as nand_spl does. Even if it's somewhat appropriate for the main u-boot, the SPL itself isn't (necessarily) ramboot, and we don't have separate configs for SPL and main u-boot. It was also inconsistent, as other platforms such as mpc83xx didn't use CONFIG_RAMBOOT in this way. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
60 lines
1.7 KiB
C
60 lines
1.7 KiB
C
/*
|
|
* Copyright 2009 Freescale Semiconductor, Inc.
|
|
*
|
|
* See file CREDITS for list of people who contributed to this
|
|
* project.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/processor.h>
|
|
#include <asm/global_data.h>
|
|
#include <asm/fsl_ifc.h>
|
|
#include <asm/io.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
void cpu_init_f(void)
|
|
{
|
|
#ifdef CONFIG_SYS_INIT_L2_ADDR
|
|
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
|
|
|
|
out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
|
|
|
|
/* set MBECCDIS=1, SBECCDIS=1 */
|
|
out_be32(&l2cache->l2errdis,
|
|
(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
|
|
|
|
/* set L2E=1 & L2SRAM=001 */
|
|
out_be32(&l2cache->l2ctl,
|
|
(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
|
|
#endif
|
|
}
|
|
|
|
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 8
|
|
#endif
|
|
|
|
void udelay(unsigned long usec)
|
|
{
|
|
u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
|
|
u32 ticks = ticks_per_usec * usec;
|
|
u32 s = mfspr(SPRN_TBRL);
|
|
|
|
while ((mfspr(SPRN_TBRL) - s) < ticks);
|
|
}
|