mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-27 21:33:44 +09:00
0a42a132a4
Add FPGA driver to support program FPGA with FPGA bitstream loading from filesystem. The driver are designed based on generic firmware loader framework. The driver can handle FPGA program operation from loading FPGA bitstream in flash to memory and then to program FPGA. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
75 lines
1.6 KiB
Plaintext
75 lines
1.6 KiB
Plaintext
/*
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* Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/dts-v1/;
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#include "socfpga_arria10_socdk.dtsi"
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/ {
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chosen {
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firmware-loader = <&fs_loader0>;
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};
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fs_loader0: fs-loader {
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u-boot,dm-pre-reloc;
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compatible = "u-boot,fs-loader";
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phandlepart = <&mmc 1>;
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};
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};
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&fpga_mgr {
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u-boot,dm-pre-reloc;
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altr,bitstream = "fit_spl_fpga.itb";
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};
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&mmc {
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u-boot,dm-pre-reloc;
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status = "okay";
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num-slots = <1>;
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cap-sd-highspeed;
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broken-cd;
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bus-width = <4>;
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};
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&eccmgr {
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sdmmca-ecc@ff8c2c00 {
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compatible = "altr,socfpga-sdmmc-ecc";
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reg = <0xff8c2c00 0x400>;
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altr,ecc-parent = <&mmc>;
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interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
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<47 IRQ_TYPE_LEVEL_HIGH>,
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<16 IRQ_TYPE_LEVEL_HIGH>,
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<48 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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/* Clock available early */
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&main_sdmmc_clk {
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u-boot,dm-pre-reloc;
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};
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&peri_sdmmc_clk {
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u-boot,dm-pre-reloc;
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};
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&sdmmc_free_clk {
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u-boot,dm-pre-reloc;
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};
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&sdmmc_clk {
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u-boot,dm-pre-reloc;
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};
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