mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 09:58:52 +09:00
![Stefano Babic](/assets/img/avatar_default.png)
Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Akshay Bhat <akshaybhat@timesys.com> CC: Ken Lin <Ken.Lin@advantech.com.tw> CC: Marek Vasut <marek.vasut@gmail.com> CC: Heiko Schocher <hs@denx.de> CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> CC: Christian Gmeiner <christian.gmeiner@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Patrick Bruenn <p.bruenn@beckhoff.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Nikita Kiryanov <nikita@compulab.co.il> CC: Otavio Salvador <otavio@ossystems.com.br> CC: "Eric Bénard" <eric@eukrea.com> CC: Jagan Teki <jagan@amarulasolutions.com> CC: Ye Li <ye.li@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Adrian Alonso <adrian.alonso@nxp.com> CC: Alison Wang <b18965@freescale.com> CC: Tim Harvey <tharvey@gateworks.com> CC: Martin Donnelly <martin.donnelly@ge.com> CC: Marcin Niestroj <m.niestroj@grinn-global.com> CC: Lukasz Majewski <lukma@denx.de> CC: Adam Ford <aford173@gmail.com> CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr> CC: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Soeren Moch <smoch@web.de> CC: Richard Hu <richard.hu@technexion.com> CC: Wig Cheng <wig.cheng@technexion.com> CC: Vanessa Maegima <vanessa.maegima@nxp.com> CC: Max Krummenacher <max.krummenacher@toradex.com> CC: Stefan Agner <stefan.agner@toradex.com> CC: Markus Niebel <Markus.Niebel@tq-group.com> CC: Breno Lima <breno.lima@nxp.com> CC: Francesco Montefoschi <francesco.montefoschi@udoo.org> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Scott Wood <oss@buserror.net> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Anatolij Gustschin <agust@denx.de> CC: Simon Glass <sjg@chromium.org> CC: "Andrew F. Davis" <afd@ti.com> CC: "Łukasz Majewski" <l.majewski@samsung.com> CC: Patrice Chotard <patrice.chotard@st.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Hans de Goede <hdegoede@redhat.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stephen Warren <swarren@nvidia.com> CC: Andre Przywara <andre.przywara@arm.com> CC: "Álvaro Fernández Rojas" <noltari@gmail.com> CC: York Sun <york.sun@nxp.com> CC: Xiaoliang Yang <xiaoliang.yang@nxp.com> CC: Chen-Yu Tsai <wens@csie.org> CC: George McCollister <george.mccollister@gmail.com> CC: Sven Ebenfeld <sven.ebenfeld@gmail.com> CC: Filip Brozovic <fbrozovic@gmail.com> CC: Petr Kulhavy <brain@jikos.cz> CC: Eric Nelson <eric@nelint.com> CC: Bai Ping <ping.bai@nxp.com> CC: Anson Huang <Anson.Huang@nxp.com> CC: Sanchayan Maity <maitysanchayan@gmail.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Patrick Delaunay <patrick.delaunay@st.com> CC: Gary Bisson <gary.bisson@boundarydevices.com> CC: Alexander Graf <agraf@suse.de> CC: u-boot@lists.denx.de Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
366 lines
8.1 KiB
C
366 lines
8.1 KiB
C
/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <div64.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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int get_clocks(void)
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{
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#ifdef CONFIG_FSL_ESDHC
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#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
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gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
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gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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#endif
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#endif
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return 0;
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}
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static u32 get_fast_plat_clk(void)
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{
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return scg_clk_get_rate(SCG_NIC0_CLK);
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}
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static u32 get_slow_plat_clk(void)
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{
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return scg_clk_get_rate(SCG_NIC1_CLK);
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}
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static u32 get_ipg_clk(void)
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{
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return scg_clk_get_rate(SCG_NIC1_BUS_CLK);
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}
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u32 get_lpuart_clk(void)
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{
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int index = 0;
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const u32 lpuart_array[] = {
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LPUART0_RBASE,
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LPUART1_RBASE,
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LPUART2_RBASE,
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LPUART3_RBASE,
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LPUART4_RBASE,
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LPUART5_RBASE,
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LPUART6_RBASE,
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LPUART7_RBASE,
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};
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const enum pcc_clk lpuart_pcc_clks[] = {
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PER_CLK_LPUART4,
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PER_CLK_LPUART5,
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PER_CLK_LPUART6,
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PER_CLK_LPUART7,
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};
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for (index = 0; index < 8; index++) {
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if (lpuart_array[index] == LPUART_BASE)
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break;
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}
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if (index < 4 || index > 7)
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return 0;
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return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]);
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}
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#ifdef CONFIG_SYS_LPI2C_IMX
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int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
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{
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/* Set parent to FIRC DIV2 clock */
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const enum pcc_clk lpi2c_pcc_clks[] = {
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PER_CLK_LPI2C4,
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PER_CLK_LPI2C5,
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PER_CLK_LPI2C6,
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PER_CLK_LPI2C7,
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};
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if (i2c_num < 4 || i2c_num > 7)
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return -EINVAL;
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if (enable) {
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pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
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pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4], SCG_FIRC_DIV2_CLK);
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pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], true);
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} else {
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pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
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}
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return 0;
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}
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u32 imx_get_i2cclk(unsigned i2c_num)
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{
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const enum pcc_clk lpi2c_pcc_clks[] = {
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PER_CLK_LPI2C4,
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PER_CLK_LPI2C5,
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PER_CLK_LPI2C6,
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PER_CLK_LPI2C7,
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};
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if (i2c_num < 4 || i2c_num > 7)
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return 0;
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return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4]);
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}
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#endif
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_ARM_CLK:
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return scg_clk_get_rate(SCG_CORE_CLK);
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case MXC_AXI_CLK:
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return get_fast_plat_clk();
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case MXC_AHB_CLK:
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return get_slow_plat_clk();
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case MXC_IPG_CLK:
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return get_ipg_clk();
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case MXC_I2C_CLK:
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return pcc_clock_get_rate(PER_CLK_LPI2C4);
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case MXC_UART_CLK:
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return get_lpuart_clk();
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case MXC_ESDHC_CLK:
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return pcc_clock_get_rate(PER_CLK_USDHC0);
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case MXC_ESDHC2_CLK:
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return pcc_clock_get_rate(PER_CLK_USDHC1);
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case MXC_DDR_CLK:
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return scg_clk_get_rate(SCG_DDR_CLK);
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default:
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printf("Unsupported mxc_clock %d\n", clk);
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break;
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}
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return 0;
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}
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void init_clk_usdhc(u32 index)
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{
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switch (index) {
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case 0:
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/*Disable the clock before configure it */
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pcc_clock_enable(PER_CLK_USDHC0, false);
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/* 158MHz / 1 = 158MHz */
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pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK);
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pcc_clock_div_config(PER_CLK_USDHC0, false, 1);
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pcc_clock_enable(PER_CLK_USDHC0, true);
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break;
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case 1:
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/*Disable the clock before configure it */
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pcc_clock_enable(PER_CLK_USDHC1, false);
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/* 158MHz / 1 = 158MHz */
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pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK);
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pcc_clock_div_config(PER_CLK_USDHC1, false, 1);
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pcc_clock_enable(PER_CLK_USDHC1, true);
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break;
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default:
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printf("Invalid index for USDHC %d\n", index);
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break;
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}
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}
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#ifdef CONFIG_MXC_OCOTP
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#define OCOTP_CTRL_PCC1_SLOT (38)
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#define OCOTP_CTRL_HIGH4K_PCC1_SLOT (39)
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void enable_ocotp_clk(unsigned char enable)
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{
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u32 val;
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/*
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* Seems the OCOTP CLOCKs have been enabled at default,
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* check its inuse flag
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*/
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val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT);
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if (!(val & PCC_INUSE_MASK))
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writel(PCC_CGC_MASK, (PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT));
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val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT);
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if (!(val & PCC_INUSE_MASK))
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writel(PCC_CGC_MASK,
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(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT));
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}
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#endif
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void enable_usboh3_clk(unsigned char enable)
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{
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if (enable) {
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pcc_clock_enable(PER_CLK_USB0, false);
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pcc_clock_sel(PER_CLK_USB0, SCG_NIC1_BUS_CLK);
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pcc_clock_enable(PER_CLK_USB0, true);
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#ifdef CONFIG_USB_MAX_CONTROLLER_COUNT
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if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) {
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pcc_clock_enable(PER_CLK_USB1, false);
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pcc_clock_sel(PER_CLK_USB1, SCG_NIC1_BUS_CLK);
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pcc_clock_enable(PER_CLK_USB1, true);
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}
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#endif
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pcc_clock_enable(PER_CLK_USB_PHY, true);
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pcc_clock_enable(PER_CLK_USB_PL301, true);
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} else {
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pcc_clock_enable(PER_CLK_USB0, false);
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pcc_clock_enable(PER_CLK_USB1, false);
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pcc_clock_enable(PER_CLK_USB_PHY, false);
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pcc_clock_enable(PER_CLK_USB_PL301, false);
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}
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}
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static void lpuart_set_clk(uint32_t index, enum scg_clk clk)
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{
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const enum pcc_clk lpuart_pcc_clks[] = {
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PER_CLK_LPUART4,
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PER_CLK_LPUART5,
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PER_CLK_LPUART6,
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PER_CLK_LPUART7,
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};
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if (index < 4 || index > 7)
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return;
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#ifndef CONFIG_CLK_DEBUG
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pcc_clock_enable(lpuart_pcc_clks[index - 4], false);
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#endif
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pcc_clock_sel(lpuart_pcc_clks[index - 4], clk);
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pcc_clock_enable(lpuart_pcc_clks[index - 4], true);
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}
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static void init_clk_lpuart(void)
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{
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u32 index = 0, i;
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const u32 lpuart_array[] = {
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LPUART0_RBASE,
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LPUART1_RBASE,
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LPUART2_RBASE,
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LPUART3_RBASE,
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LPUART4_RBASE,
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LPUART5_RBASE,
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LPUART6_RBASE,
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LPUART7_RBASE,
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};
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for (i = 0; i < 8; i++) {
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if (lpuart_array[i] == LPUART_BASE) {
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index = i;
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break;
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}
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}
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lpuart_set_clk(index, SCG_SOSC_DIV2_CLK);
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}
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static void init_clk_rgpio2p(void)
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{
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/*Enable RGPIO2P1 clock */
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pcc_clock_enable(PER_CLK_RGPIO2P1, true);
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/*
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* Hard code to enable RGPIO2P0 clock since it is not
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* in clock frame for A7 domain
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*/
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writel(PCC_CGC_MASK, (PCC0_RBASE + 0x3C));
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}
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/* Configure PLL/PFD freq */
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void clock_init(void)
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{
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/*
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* ROM has enabled clocks:
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* A4 side: SIRC 16Mhz (DIV1-3 off), FIRC 48Mhz (DIV1-2 on),
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* Non-LP-boot: SOSC, SPLL PFD0 (scs selected)
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* A7 side: SPLL PFD0 (scs selected, 413Mhz),
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* APLL PFD0 (352Mhz), DDRCLK, all NIC clocks
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* A7 Plat0 (NIC0) = 176Mhz, Plat1 (NIC1) = 176Mhz,
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* IP BUS (NIC1_BUS) = 58.6Mhz
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*
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* In u-boot:
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* 1. Enable PFD1-3 of APLL for A7 side. Enable FIRC and DIVs.
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* 2. Enable USB PLL
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* 3. Init the clocks of peripherals used in u-boot bu
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* without set rate interface.The clocks for these
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* peripherals are enabled in this intialization.
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* 4.Other peripherals with set clock rate interface
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* does not be set in this function.
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*/
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scg_a7_firc_init();
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scg_a7_soscdiv_init();
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/* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */
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scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
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scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 20);
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scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
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init_clk_lpuart();
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init_clk_rgpio2p();
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enable_usboh3_clk(1);
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}
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#ifdef CONFIG_SECURE_BOOT
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void hab_caam_clock_enable(unsigned char enable)
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{
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if (enable)
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pcc_clock_enable(PER_CLK_CAAM, true);
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else
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pcc_clock_enable(PER_CLK_CAAM, false);
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}
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#endif
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/*
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* Dump some core clockes.
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*/
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int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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u32 addr = 0;
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u32 freq;
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freq = decode_pll(PLL_A7_SPLL);
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printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000);
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freq = decode_pll(PLL_A7_APLL);
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printf("PLL_A7_APLL %8d MHz\n", freq / 1000000);
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freq = decode_pll(PLL_USB);
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printf("PLL_USB %8d MHz\n", freq / 1000000);
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printf("\n");
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printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000);
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printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
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printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
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printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
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printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
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printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
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printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
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printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
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printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000);
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addr = (u32) clock_init;
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printf("[%s] addr = 0x%08X\r\n", __func__, addr);
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scg_a7_info();
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return 0;
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}
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U_BOOT_CMD(
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clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
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"display clocks",
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""
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);
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