mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-17 08:39:17 +09:00
14e4b14979
Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
30 lines
638 B
Plaintext
30 lines
638 B
Plaintext
if ARCH_ASPEED
|
|
|
|
config SYS_ARCH
|
|
default "arm"
|
|
|
|
config SYS_SOC
|
|
default "aspeed"
|
|
|
|
config SYS_TEXT_BASE
|
|
default 0x00000000
|
|
|
|
config ASPEED_AST2500
|
|
bool "Support Aspeed AST2500 SoC"
|
|
select CPU_ARM1176
|
|
help
|
|
The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU.
|
|
It is used as Board Management Controller on many server boards,
|
|
which is enabled by support of LPC and eSPI peripherals.
|
|
|
|
config WDT_NUM
|
|
int "Number of Watchdog Timers"
|
|
default 3 if ASPEED_AST2500
|
|
help
|
|
The number of Watchdot Timers on a SoC.
|
|
AST2500 has three WDTsk earlier versions have two or fewer.
|
|
|
|
source "arch/arm/mach-aspeed/ast2500/Kconfig"
|
|
|
|
endif
|