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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
210 lines
5.5 KiB
C
210 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* sun9i specific clock code
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*
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* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
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*
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* (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
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* Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/prcm.h>
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#include <asm/arch/sys_proto.h>
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#ifdef CONFIG_SPL_BUILD
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void clock_init_safe(void)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* Set up PLL12 (peripheral 1) */
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clock_set_pll12(1200000000);
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/* Set up PLL1 (cluster 0) and PLL2 (cluster 1) */
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clock_set_pll1(408000000);
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clock_set_pll2(408000000);
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/* Set up PLL4 (peripheral 0) */
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clock_set_pll4(960000000);
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/* Set up dividers for AXI0 and APB0 on cluster 0: PLL1 / 2 = 204MHz */
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writel(C0_CFG_AXI0_CLK_DIV_RATIO(2) |
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C0_CFG_APB0_CLK_DIV_RATIO(2), &ccm->c0_cfg);
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/* AHB0: 120 MHz (PLL_PERIPH0 / 8) */
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writel(AHBx_SRC_PLL_PERIPH0 | AHBx_CLK_DIV_RATIO(8),
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&ccm->ahb0_cfg);
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/* AHB1: 240 MHz (PLL_PERIPH0 / 4) */
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writel(AHBx_SRC_PLL_PERIPH0 | AHBx_CLK_DIV_RATIO(4),
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&ccm->ahb1_cfg);
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/* AHB2: 120 MHz (PLL_PERIPH0 / 8) */
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writel(AHBx_SRC_PLL_PERIPH0 | AHBx_CLK_DIV_RATIO(8),
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&ccm->ahb2_cfg);
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/* APB0: 120 MHz (PLL_PERIPH0 / 8) */
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writel(APB0_SRC_PLL_PERIPH0 | APB0_CLK_DIV_RATIO(8),
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&ccm->apb0_cfg);
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/* GTBUS: 400MHz (PERIPH0 div 3) */
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writel(GTBUS_SRC_PLL_PERIPH1 | GTBUS_CLK_DIV_RATIO(3),
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&ccm->gtbus_cfg);
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/* CCI400: 480MHz (PERIPH1 div 2) */
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writel(CCI400_SRC_PLL_PERIPH0 | CCI400_CLK_DIV_RATIO(2),
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&ccm->cci400_cfg);
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/* Deassert DMA reset and open clock gating for DMA */
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setbits_le32(&ccm->ahb_reset1_cfg, (1 << 24));
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setbits_le32(&ccm->apb1_gate, (1 << 24));
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/* set enable-bit in TSTAMP_CTRL_REG */
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writel(1, 0x01720000);
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}
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#endif
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void clock_init_uart(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* open the clock for uart */
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setbits_le32(&ccm->apb1_gate,
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CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
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CONFIG_CONS_INDEX - 1));
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/* deassert uart reset */
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setbits_le32(&ccm->apb1_reset_cfg,
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1 << (APB1_RESET_UART_SHIFT +
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CONFIG_CONS_INDEX - 1));
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}
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#ifdef CONFIG_SPL_BUILD
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void clock_set_pll1(unsigned int clk)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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const int p = 0;
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/* Switch cluster 0 to 24MHz clock while changing PLL1 */
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clrsetbits_le32(&ccm->cpu_clk_source, C0_CPUX_CLK_SRC_MASK,
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C0_CPUX_CLK_SRC_OSC24M);
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writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
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CCM_PLL1_CLOCK_TIME_2 |
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CCM_PLL1_CTRL_N(clk / 24000000),
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&ccm->pll1_c0_cfg);
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/*
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* Don't bother with the stable-time registers, as it doesn't
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* wait until the PLL is stable. Note, that even Allwinner
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* just uses a delay loop (or rather the AVS timer) for this
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* instead of the PLL_STABLE_STATUS register.
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*/
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sdelay(2000);
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/* Switch cluster 0 back to PLL1 */
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clrsetbits_le32(&ccm->cpu_clk_source, C0_CPUX_CLK_SRC_MASK,
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C0_CPUX_CLK_SRC_PLL1);
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}
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void clock_set_pll2(unsigned int clk)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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const int p = 0;
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/* Switch cluster 1 to 24MHz clock while changing PLL2 */
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clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK,
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C1_CPUX_CLK_SRC_OSC24M);
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writel(CCM_PLL2_CTRL_EN | CCM_PLL2_CTRL_P(p) |
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CCM_PLL2_CLOCK_TIME_2 | CCM_PLL2_CTRL_N(clk / 24000000),
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&ccm->pll2_c1_cfg);
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sdelay(2000);
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/* Switch cluster 1 back to PLL2 */
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clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK,
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C1_CPUX_CLK_SRC_PLL2);
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}
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void clock_set_pll6(unsigned int clk)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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const int p = 0;
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writel(CCM_PLL6_CTRL_EN | CCM_PLL6_CFG_UPDATE | CCM_PLL6_CTRL_P(p)
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| CCM_PLL6_CTRL_N(clk / 24000000),
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&ccm->pll6_ddr_cfg);
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do { } while (!(readl(&ccm->pll_stable_status) & PLL_DDR_STATUS));
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sdelay(2000);
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}
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void clock_set_pll12(unsigned int clk)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN)
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return;
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writel(CCM_PLL12_CTRL_EN | CCM_PLL12_CTRL_N(clk / 24000000),
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&ccm->pll12_periph1_cfg);
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sdelay(2000);
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}
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void clock_set_pll4(unsigned int clk)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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writel(CCM_PLL4_CTRL_EN | CCM_PLL4_CTRL_N(clk / 24000000),
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&ccm->pll4_periph0_cfg);
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sdelay(2000);
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}
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#endif
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int clock_twi_onoff(int port, int state)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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if (port > 4)
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return -1;
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/* set the apb reset and clock gate for twi */
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if (state) {
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setbits_le32(&ccm->apb1_gate,
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CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
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setbits_le32(&ccm->apb1_reset_cfg,
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1 << (APB1_RESET_TWI_SHIFT + port));
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} else {
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clrbits_le32(&ccm->apb1_reset_cfg,
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1 << (APB1_RESET_TWI_SHIFT + port));
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clrbits_le32(&ccm->apb1_gate,
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CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
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}
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return 0;
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}
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unsigned int clock_get_pll4_periph0(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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uint32_t rval = readl(&ccm->pll4_periph0_cfg);
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int n = ((rval & CCM_PLL4_CTRL_N_MASK) >> CCM_PLL4_CTRL_N_SHIFT);
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int p = ((rval & CCM_PLL4_CTRL_P_MASK) >> CCM_PLL4_CTRL_P_SHIFT);
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int m = ((rval & CCM_PLL4_CTRL_M_MASK) >> CCM_PLL4_CTRL_M_SHIFT) + 1;
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const int k = 1;
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return ((24000000 * n * k) >> p) / m;
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}
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