mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-28 21:09:00 +09:00
![Heiko Stuebner](/assets/img/avatar_default.png)
This is the state as of v5.10 + the recently added timer0 phandle targetted at the 5.12 merge window. With this the non-mainline nodes like the dmc move to a separate rk3368-u-boot.dtsi that is included from the board-specific -u-boot.dtsi files, similar to how rk3399 does this. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
74 lines
1.1 KiB
Plaintext
74 lines
1.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
/*
|
|
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
|
|
*/
|
|
|
|
#include "rk3368-u-boot.dtsi"
|
|
|
|
/ {
|
|
chosen {
|
|
u-boot,spl-boot-order = &emmc;
|
|
};
|
|
};
|
|
|
|
&dmc {
|
|
u-boot,dm-pre-reloc;
|
|
|
|
/*
|
|
* PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct
|
|
* See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
|
|
* details on the 'rockchip,memory-schedule' property and how it
|
|
* affects the physical-address to device-address mapping.
|
|
*/
|
|
rockchip,memory-schedule = <DMC_MSCH_CBRD>;
|
|
rockchip,ddr-frequency = <800000000>;
|
|
rockchip,ddr-speed-bin = <DDR3_1600K>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
&pinctrl {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&service_msch {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&dmc {
|
|
u-boot,dm-pre-reloc;
|
|
status = "okay";
|
|
};
|
|
|
|
&pmugrf {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&sgrf {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&cru {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&grf {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&uart4 {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&emmc {
|
|
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
|
|
u-boot,spl-fifo-mode;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&timer0 {
|
|
u-boot,dm-pre-reloc;
|
|
clock-frequency = <24000000>;
|
|
status = "okay";
|
|
};
|