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![Frank Wunderlich](/assets/img/avatar_default.png)
Add DTS nodes for MT7622/BPI-R64 Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
255 lines
4.1 KiB
Plaintext
255 lines
4.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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/dts-v1/;
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#include "mt7622.dtsi"
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#include "mt7622-u-boot.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "mt7622-bpi-r64";
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compatible = "mediatek,mt7622", "mediatek,mt7622-rfb";
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chosen {
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stdout-path = &uart0;
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tick-timer = &timer0;
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};
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aliases {
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spi0 = &snfi;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x40000000 0x40000000>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
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status = "okay";
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pcie@0,0 {
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status = "okay";
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};
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pcie@1,0 {
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status = "okay";
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};
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};
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&pinctrl {
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pcie0_pins: pcie0-pins {
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mux {
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function = "pcie";
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groups = "pcie0_pad_perst",
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"pcie0_1_waken",
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"pcie0_1_clkreq";
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};
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};
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pcie1_pins: pcie1-pins {
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mux {
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function = "pcie";
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groups = "pcie1_pad_perst",
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"pcie1_0_waken",
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"pcie1_0_clkreq";
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};
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};
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snfi_pins: snfi-pins {
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mux {
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function = "flash";
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groups = "snfi";
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};
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};
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snor_pins: snor-pins {
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mux {
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function = "flash";
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groups = "spi_nor";
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};
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};
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uart0_pins: uart0 {
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mux {
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function = "uart";
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groups = "uart0_0_tx_rx" ;
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};
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};
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pwm_pins: pwm1 {
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mux {
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function = "pwm";
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groups = "pwm_ch1_0" ;
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};
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};
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watchdog_pins: watchdog-default {
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mux {
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function = "watchdog";
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groups = "watchdog";
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};
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};
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mmc0_pins_default: mmc0default {
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mux {
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function = "emmc";
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groups = "emmc";
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};
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/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
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* "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
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* DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
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*/
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conf-cmd-dat {
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pins = "NDL0", "NDL1", "NDL2",
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"NDL3", "NDL4", "NDL5",
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"NDL6", "NDL7", "NRB";
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input-enable;
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bias-pull-up;
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};
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conf-clk {
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pins = "NCLE";
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bias-pull-down;
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};
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};
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mmc1_pins_default: mmc1default {
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mux {
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function = "sd";
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groups = "sd_0";
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};
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/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
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* "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
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* DAT2, DAT3, CMD, CLK for SD respectively.
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*/
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conf-cmd-data {
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pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
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"I2S2_IN","I2S4_OUT";
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input-enable;
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drive-strength = <8>;
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bias-pull-up;
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};
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conf-clk {
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pins = "I2S3_OUT";
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drive-strength = <12>;
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bias-pull-down;
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};
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conf-cd {
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pins = "TXD3";
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bias-pull-up;
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};
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};
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};
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&snfi {
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pinctrl-names = "default", "snfi";
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pinctrl-0 = <&snor_pins>;
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pinctrl-1 = <&snfi_pins>;
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status = "okay";
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spi-flash@0{
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compatible = "jedec,spi-nor";
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reg = <0>;
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u-boot,dm-pre-reloc;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm_pins>;
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status = "okay";
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins_default>;
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status = "okay";
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bus-width = <8>;
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max-frequency = <50000000>;
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cap-sd-highspeed;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_3p3v>;
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non-removable;
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};
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&mmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins_default>;
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status = "okay";
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bus-width = <4>;
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max-frequency = <50000000>;
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cap-sd-highspeed;
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r_smpl = <1>;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_3p3v>;
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};
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&watchdog {
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pinctrl-names = "default";
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pinctrl-0 = <&watchdog_pins>;
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status = "okay";
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};
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ð {
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status = "okay";
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mediatek,gmac-id = <0>;
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phy-mode = "sgmii";
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mediatek,switch = "mt7531";
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reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&gpio {
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/*gpio 90 for setting mode to sata*/
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asm_sel {
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gpio-hog;
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gpios = <90 GPIO_ACTIVE_HIGH>;
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output-low;
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};
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};
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&ssusb {
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status = "okay";
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};
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&u3phy {
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status = "okay";
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};
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