mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-28 21:09:00 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
502 lines
14 KiB
C
502 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Google Inc.
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*
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* Extracted from Chromium coreboot commit 3f59b13d
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*/
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#include <common.h>
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#include <dm.h>
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#include <edid.h>
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#include <errno.h>
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#include <display.h>
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#include <edid.h>
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#include <lcd.h>
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#include <video.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/pwm.h>
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#include <asm/arch-tegra/dc.h>
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#include <dm/uclass-internal.h>
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#include "displayport.h"
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/* return in 1000ths of a Hertz */
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static int tegra_dc_calc_refresh(const struct display_timing *timing)
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{
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int h_total, v_total, refresh;
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int pclk = timing->pixelclock.typ;
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h_total = timing->hactive.typ + timing->hfront_porch.typ +
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timing->hback_porch.typ + timing->hsync_len.typ;
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v_total = timing->vactive.typ + timing->vfront_porch.typ +
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timing->vback_porch.typ + timing->vsync_len.typ;
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if (!pclk || !h_total || !v_total)
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return 0;
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refresh = pclk / h_total;
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refresh *= 1000;
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refresh /= v_total;
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return refresh;
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}
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static void print_mode(const struct display_timing *timing)
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{
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int refresh = tegra_dc_calc_refresh(timing);
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debug("MODE:%dx%d@%d.%03uHz pclk=%d\n",
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timing->hactive.typ, timing->vactive.typ, refresh / 1000,
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refresh % 1000, timing->pixelclock.typ);
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}
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static int update_display_mode(struct dc_ctlr *disp_ctrl,
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const struct display_timing *timing,
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int href_to_sync, int vref_to_sync)
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{
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print_mode(timing);
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writel(0x1, &disp_ctrl->disp.disp_timing_opt);
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writel(vref_to_sync << 16 | href_to_sync,
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&disp_ctrl->disp.ref_to_sync);
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writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ,
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&disp_ctrl->disp.sync_width);
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writel(((timing->vback_porch.typ - vref_to_sync) << 16) |
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timing->hback_porch.typ, &disp_ctrl->disp.back_porch);
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writel(((timing->vfront_porch.typ + vref_to_sync) << 16) |
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timing->hfront_porch.typ, &disp_ctrl->disp.front_porch);
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writel(timing->hactive.typ | (timing->vactive.typ << 16),
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&disp_ctrl->disp.disp_active);
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/**
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* We want to use PLLD_out0, which is PLLD / 2:
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* PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv.
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*
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* Currently most panels work inside clock range 50MHz~100MHz, and PLLD
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* has some requirements to have VCO in range 500MHz~1000MHz (see
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* clock.c for more detail). To simplify calculation, we set
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* PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values
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* may be calculated by clock_display, to allow wider frequency range.
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*
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* Note ShiftClockDiv is a 7.1 format value.
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*/
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const u32 shift_clock_div = 1;
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writel((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) |
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((shift_clock_div - 1) * 2) << SHIFT_CLK_DIVIDER_SHIFT,
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&disp_ctrl->disp.disp_clk_ctrl);
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debug("%s: PixelClock=%u, ShiftClockDiv=%u\n", __func__,
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timing->pixelclock.typ, shift_clock_div);
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return 0;
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}
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static u32 tegra_dc_poll_register(void *reg,
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u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us)
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{
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u32 temp = timeout_us;
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u32 reg_val = 0;
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do {
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udelay(poll_interval_us);
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reg_val = readl(reg);
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if (timeout_us > poll_interval_us)
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timeout_us -= poll_interval_us;
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else
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break;
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} while ((reg_val & mask) != exp_val);
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if ((reg_val & mask) == exp_val)
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return 0; /* success */
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return temp;
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}
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int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl)
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{
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writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
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if (tegra_dc_poll_register(&disp_ctrl->cmd.state_ctrl,
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GENERAL_ACT_REQ, 0, 100,
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DC_POLL_TIMEOUT_MS * 1000)) {
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debug("dc timeout waiting for DC to stop\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static struct display_timing min_mode = {
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.hsync_len = { .typ = 1 },
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.vsync_len = { .typ = 1 },
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.hback_porch = { .typ = 20 },
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.vback_porch = { .typ = 0 },
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.hactive = { .typ = 16 },
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.vactive = { .typ = 16 },
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.hfront_porch = { .typ = 1 },
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.vfront_porch = { .typ = 2 },
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};
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/* Disable windows and set minimum raster timings */
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void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl,
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int *dc_reg_ctx)
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{
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const int href_to_sync = 0, vref_to_sync = 1;
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int selected_windows, i;
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selected_windows = readl(&disp_ctrl->cmd.disp_win_header);
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/* Store and clear window options */
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for (i = 0; i < DC_N_WINDOWS; ++i) {
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writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
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dc_reg_ctx[i] = readl(&disp_ctrl->win.win_opt);
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writel(0, &disp_ctrl->win.win_opt);
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writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
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}
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writel(selected_windows, &disp_ctrl->cmd.disp_win_header);
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/* Store current raster timings and set minimum timings */
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dc_reg_ctx[i++] = readl(&disp_ctrl->disp.ref_to_sync);
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writel(href_to_sync | (vref_to_sync << 16),
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&disp_ctrl->disp.ref_to_sync);
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dc_reg_ctx[i++] = readl(&disp_ctrl->disp.sync_width);
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writel(min_mode.hsync_len.typ | (min_mode.vsync_len.typ << 16),
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&disp_ctrl->disp.sync_width);
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dc_reg_ctx[i++] = readl(&disp_ctrl->disp.back_porch);
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writel(min_mode.hback_porch.typ | (min_mode.vback_porch.typ << 16),
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&disp_ctrl->disp.back_porch);
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dc_reg_ctx[i++] = readl(&disp_ctrl->disp.front_porch);
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writel(min_mode.hfront_porch.typ | (min_mode.vfront_porch.typ << 16),
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&disp_ctrl->disp.front_porch);
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dc_reg_ctx[i++] = readl(&disp_ctrl->disp.disp_active);
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writel(min_mode.hactive.typ | (min_mode.vactive.typ << 16),
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&disp_ctrl->disp.disp_active);
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writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
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}
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/* Restore previous windows status and raster timings */
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void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl,
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int *dc_reg_ctx)
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{
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int selected_windows, i;
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selected_windows = readl(&disp_ctrl->cmd.disp_win_header);
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for (i = 0; i < DC_N_WINDOWS; ++i) {
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writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
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writel(dc_reg_ctx[i], &disp_ctrl->win.win_opt);
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writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
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}
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writel(selected_windows, &disp_ctrl->cmd.disp_win_header);
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writel(dc_reg_ctx[i++], &disp_ctrl->disp.ref_to_sync);
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writel(dc_reg_ctx[i++], &disp_ctrl->disp.sync_width);
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writel(dc_reg_ctx[i++], &disp_ctrl->disp.back_porch);
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writel(dc_reg_ctx[i++], &disp_ctrl->disp.front_porch);
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writel(dc_reg_ctx[i++], &disp_ctrl->disp.disp_active);
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writel(GENERAL_UPDATE, &disp_ctrl->cmd.state_ctrl);
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}
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static int tegra_depth_for_bpp(int bpp)
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{
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switch (bpp) {
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case 32:
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return COLOR_DEPTH_R8G8B8A8;
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case 16:
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return COLOR_DEPTH_B5G6R5;
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default:
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debug("Unsupported LCD bit depth");
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return -1;
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}
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}
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static int update_window(struct dc_ctlr *disp_ctrl,
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u32 frame_buffer, int fb_bits_per_pixel,
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const struct display_timing *timing)
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{
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const u32 colour_white = 0xffffff;
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int colour_depth;
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u32 val;
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writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
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writel(((timing->vactive.typ << 16) | timing->hactive.typ),
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&disp_ctrl->win.size);
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writel(((timing->vactive.typ << 16) |
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(timing->hactive.typ * fb_bits_per_pixel / 8)),
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&disp_ctrl->win.prescaled_size);
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writel(((timing->hactive.typ * fb_bits_per_pixel / 8 + 31) /
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32 * 32), &disp_ctrl->win.line_stride);
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colour_depth = tegra_depth_for_bpp(fb_bits_per_pixel);
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if (colour_depth == -1)
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return -EINVAL;
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writel(colour_depth, &disp_ctrl->win.color_depth);
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writel(frame_buffer, &disp_ctrl->winbuf.start_addr);
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writel(0x1000 << V_DDA_INC_SHIFT | 0x1000 << H_DDA_INC_SHIFT,
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&disp_ctrl->win.dda_increment);
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writel(colour_white, &disp_ctrl->disp.blend_background_color);
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writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
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&disp_ctrl->cmd.disp_cmd);
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writel(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
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val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
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val |= GENERAL_UPDATE | WIN_A_UPDATE;
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writel(val, &disp_ctrl->cmd.state_ctrl);
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/* Enable win_a */
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val = readl(&disp_ctrl->win.win_opt);
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writel(val | WIN_ENABLE, &disp_ctrl->win.win_opt);
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return 0;
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}
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static int tegra_dc_init(struct dc_ctlr *disp_ctrl)
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{
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/* do not accept interrupts during initialization */
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writel(0x00000000, &disp_ctrl->cmd.int_mask);
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writel(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
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&disp_ctrl->cmd.state_access);
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writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
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writel(0x00000000, &disp_ctrl->win.win_opt);
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writel(0x00000000, &disp_ctrl->win.byte_swap);
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writel(0x00000000, &disp_ctrl->win.buffer_ctrl);
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writel(0x00000000, &disp_ctrl->win.pos);
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writel(0x00000000, &disp_ctrl->win.h_initial_dda);
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writel(0x00000000, &disp_ctrl->win.v_initial_dda);
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writel(0x00000000, &disp_ctrl->win.dda_increment);
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writel(0x00000000, &disp_ctrl->win.dv_ctrl);
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writel(0x01000000, &disp_ctrl->win.blend_layer_ctrl);
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writel(0x00000000, &disp_ctrl->win.blend_match_select);
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writel(0x00000000, &disp_ctrl->win.blend_nomatch_select);
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writel(0x00000000, &disp_ctrl->win.blend_alpha_1bit);
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writel(0x00000000, &disp_ctrl->winbuf.start_addr_hi);
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writel(0x00000000, &disp_ctrl->winbuf.addr_h_offset);
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writel(0x00000000, &disp_ctrl->winbuf.addr_v_offset);
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writel(0x00000000, &disp_ctrl->com.crc_checksum);
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writel(0x00000000, &disp_ctrl->com.pin_output_enb[0]);
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writel(0x00000000, &disp_ctrl->com.pin_output_enb[1]);
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writel(0x00000000, &disp_ctrl->com.pin_output_enb[2]);
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writel(0x00000000, &disp_ctrl->com.pin_output_enb[3]);
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writel(0x00000000, &disp_ctrl->disp.disp_signal_opt0);
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return 0;
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}
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static void dump_config(int panel_bpp, struct display_timing *timing)
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{
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printf("timing->hactive.typ = %d\n", timing->hactive.typ);
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printf("timing->vactive.typ = %d\n", timing->vactive.typ);
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printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ);
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printf("timing->hfront_porch.typ = %d\n", timing->hfront_porch.typ);
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printf("timing->hsync_len.typ = %d\n", timing->hsync_len.typ);
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printf("timing->hback_porch.typ = %d\n", timing->hback_porch.typ);
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printf("timing->vfront_porch.typ %d\n", timing->vfront_porch.typ);
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printf("timing->vsync_len.typ = %d\n", timing->vsync_len.typ);
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printf("timing->vback_porch.typ = %d\n", timing->vback_porch.typ);
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printf("panel_bits_per_pixel = %d\n", panel_bpp);
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}
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static int display_update_config_from_edid(struct udevice *dp_dev,
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int *panel_bppp,
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struct display_timing *timing)
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{
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return display_read_timing(dp_dev, timing);
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}
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static int display_init(struct udevice *dev, void *lcdbase,
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int fb_bits_per_pixel, struct display_timing *timing)
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{
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struct display_plat *disp_uc_plat;
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struct dc_ctlr *dc_ctlr;
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struct udevice *dp_dev;
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const int href_to_sync = 1, vref_to_sync = 1;
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int panel_bpp = 18; /* default 18 bits per pixel */
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u32 plld_rate;
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int ret;
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/*
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* Before we probe the display device (eDP), tell it that this device
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* is the source of the display data.
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*/
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ret = uclass_find_first_device(UCLASS_DISPLAY, &dp_dev);
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if (ret) {
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debug("%s: device '%s' display not found (ret=%d)\n", __func__,
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dev->name, ret);
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return ret;
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}
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disp_uc_plat = dev_get_uclass_platdata(dp_dev);
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debug("Found device '%s', disp_uc_priv=%p\n", dp_dev->name,
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disp_uc_plat);
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disp_uc_plat->src_dev = dev;
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ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev);
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if (ret) {
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debug("%s: Failed to probe eDP, ret=%d\n", __func__, ret);
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return ret;
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}
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dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev);
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if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
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debug("%s: Failed to decode display timing\n", __func__);
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return -EINVAL;
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}
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ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing);
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if (ret) {
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debug("%s: Failed to decode EDID, using defaults\n", __func__);
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dump_config(panel_bpp, timing);
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}
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/*
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* The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
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* and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
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* update_display_mode() for detail.
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*/
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plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2);
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if (plld_rate == 0) {
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printf("dc: clock init failed\n");
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return -EIO;
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} else if (plld_rate != timing->pixelclock.typ * 2) {
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debug("dc: plld rounded to %u\n", plld_rate);
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timing->pixelclock.typ = plld_rate / 2;
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}
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/* Init dc */
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ret = tegra_dc_init(dc_ctlr);
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if (ret) {
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debug("dc: init failed\n");
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return ret;
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}
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/* Configure dc mode */
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ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync);
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if (ret) {
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debug("dc: failed to configure display mode\n");
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return ret;
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}
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/* Enable dp */
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ret = display_enable(dp_dev, panel_bpp, timing);
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if (ret) {
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debug("dc: failed to enable display: ret=%d\n", ret);
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return ret;
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}
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ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing);
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if (ret) {
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debug("dc: failed to update window\n");
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return ret;
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}
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debug("%s: ready\n", __func__);
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return 0;
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}
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enum {
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/* Maximum LCD size we support */
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LCD_MAX_WIDTH = 1920,
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LCD_MAX_HEIGHT = 1200,
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LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */
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};
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static int tegra124_lcd_init(struct udevice *dev, void *lcdbase,
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enum video_log2_bpp l2bpp)
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{
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct display_timing timing;
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int ret;
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clock_set_up_plldp();
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clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000);
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|
clock_enable(PERIPH_ID_HOST1X);
|
|
clock_enable(PERIPH_ID_DISP1);
|
|
clock_enable(PERIPH_ID_PWM);
|
|
clock_enable(PERIPH_ID_DPAUX);
|
|
clock_enable(PERIPH_ID_SOR0);
|
|
udelay(2);
|
|
|
|
reset_set_enable(PERIPH_ID_HOST1X, 0);
|
|
reset_set_enable(PERIPH_ID_DISP1, 0);
|
|
reset_set_enable(PERIPH_ID_PWM, 0);
|
|
reset_set_enable(PERIPH_ID_DPAUX, 0);
|
|
reset_set_enable(PERIPH_ID_SOR0, 0);
|
|
|
|
ret = display_init(dev, lcdbase, 1 << l2bpp, &timing);
|
|
if (ret)
|
|
return ret;
|
|
|
|
uc_priv->xsize = roundup(timing.hactive.typ, 16);
|
|
uc_priv->ysize = timing.vactive.typ;
|
|
uc_priv->bpix = l2bpp;
|
|
|
|
video_set_flush_dcache(dev, 1);
|
|
debug("%s: done\n", __func__);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra124_lcd_probe(struct udevice *dev)
|
|
{
|
|
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
|
|
ulong start;
|
|
int ret;
|
|
|
|
start = get_timer(0);
|
|
bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "lcd");
|
|
ret = tegra124_lcd_init(dev, (void *)plat->base, VIDEO_BPP16);
|
|
bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
|
|
debug("LCD init took %lu ms\n", get_timer(start));
|
|
if (ret)
|
|
printf("%s: Error %d\n", __func__, ret);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra124_lcd_bind(struct udevice *dev)
|
|
{
|
|
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
|
|
|
|
uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
|
|
(1 << VIDEO_BPP16) / 8;
|
|
debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id tegra124_lcd_ids[] = {
|
|
{ .compatible = "nvidia,tegra124-dc" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(tegra124_dc) = {
|
|
.name = "tegra124-dc",
|
|
.id = UCLASS_VIDEO,
|
|
.of_match = tegra124_lcd_ids,
|
|
.bind = tegra124_lcd_bind,
|
|
.probe = tegra124_lcd_probe,
|
|
};
|