mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 21:26:19 +09:00
195dc23185
Update igep00x0 code with the following features: - Add board and revision detection for the boards: - IGEP0020-RF - IGEP0020-RC - IGEP0030-RG - IGEP0030-RE - Merge IGEP0020 and IGEP0030 mux tables - Add suport to use GPIO_126, GPIO_127 and GPIO_129 - board_name and board_rev environment variables display board and revision informations - Move dtb name selection from code to boot script Signed-off-by: Pau Pajuelo <ppajuel@gmail.com> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
69 lines
1.4 KiB
C
69 lines
1.4 KiB
C
/*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <twl4030.h>
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#include <asm/io.h>
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#include <asm/omap_mmc.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <jffs2/load_kernel.h>
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#include <linux/mtd/nand.h>
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#include "igep00x0.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_DEFAULT();
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}
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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int loops = 100;
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/* find out flash memory type, assume NAND first */
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gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
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gpmc_init();
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/* Issue a RESET and then READID */
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writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
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writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
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while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
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!= NAND_STATUS_READY) {
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udelay(1);
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if (--loops == 0) {
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gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
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gpmc_init(); /* reinitialize for OneNAND */
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break;
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}
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}
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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return 0;
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}
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#if defined(CONFIG_MMC)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, -1, -1);
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}
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void board_mmc_power_init(void)
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{
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twl4030_power_mmc_init(0);
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}
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#endif
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