mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-02 08:13:44 +09:00
b6ceefedf7
Due to the introduction of the pinctrl and clk driver, and using device tree files, remove the unneeded hardcoded pin configuration and clock enabling code from the board file. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Remove CONFIG_PHY_MICREL as per previous patch: Signed-off-by: Simon Glass <sjg@chromium.org>
157 lines
4.1 KiB
C
157 lines
4.1 KiB
C
/*
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* Configuation settings for the SAMA5D3xEK board.
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*
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* Copyright (C) 2012 - 2013 Atmel
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*
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* based on at91sam9m10g45ek.h by:
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include "at91-sama5_common.h"
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#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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/*
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* This needs to be defined for the OHCI code to work but it is defined as
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* ATMEL_ID_UHPHS in the CPU specific header files.
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*/
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#define ATMEL_ID_UHP ATMEL_ID_UHPHS
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/*
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* Specify the clock enable bit in the PMC_SCER register.
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*/
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#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
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/* LCD */
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#define LCD_BPP LCD_COLOR16
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#define LCD_OUTPUT_BPP 24
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#define CONFIG_LCD_LOGO
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#define CONFIG_LCD_INFO
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#define CONFIG_LCD_INFO_BELOW_LOGO
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#define CONFIG_SYS_WHITE_ON_BLACK
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#define CONFIG_ATMEL_HLCD
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#define CONFIG_ATMEL_LCD_RGB565
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/* board specific (not enough SRAM) */
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#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000
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/* NOR flash */
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#ifdef CONFIG_MTD_NOR_FLASH
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_FLASH_BASE 0x10000000
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#define CONFIG_SYS_MAX_FLASH_SECT 131
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#endif
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
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#define CONFIG_SYS_SDRAM_SIZE 0x20000000
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_INIT_SP_ADDR 0x318000
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#else
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
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#endif
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/* SerialFlash */
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#ifdef CONFIG_CMD_SF
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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#endif
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/* NAND flash */
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#define CONFIG_CMD_NAND
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/* PMECC & PMERRLOC */
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#define CONFIG_ATMEL_NAND_HWECC
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#define CONFIG_ATMEL_NAND_HW_PMECC
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#define CONFIG_PMECC_CAP 4
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#define CONFIG_PMECC_SECTOR_SIZE 512
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#define CONFIG_CMD_NAND_TRIMFFS
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#endif
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#define CONFIG_PHY_MICREL_KSZ9021
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/* USB */
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
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#endif
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#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
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#define CONFIG_FAT_WRITE
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#endif
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#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
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#ifdef CONFIG_SYS_USE_SERIALFLASH
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/* override the bootcmd, bootargs and other configuration for spi flash env*/
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#elif CONFIG_SYS_USE_NANDFLASH
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/* override the bootcmd, bootargs and other configuration nandflash env */
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#elif CONFIG_SYS_USE_MMC
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/* override the bootcmd, bootargs and other configuration for sd/mmc env */
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#else
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#define CONFIG_ENV_IS_NOWHERE
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#endif
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/* SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x300000
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#define CONFIG_SPL_MAX_SIZE 0x18000
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#define CONFIG_SPL_BSS_START_ADDR 0x20000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SYS_MONITOR_LEN (512 << 10)
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#ifdef CONFIG_SYS_USE_MMC
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#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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#elif CONFIG_SYS_USE_NANDFLASH
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
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#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
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#elif CONFIG_SYS_USE_SERIALFLASH
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
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#endif
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#endif
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