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![Peter Tyser](/assets/img/avatar_default.png)
Initial support for Extreme Engineering Solutions XPedite5170 - a MPC8640-based 3U VPX single board computer with a PMC/XMC site. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
169 lines
4.8 KiB
C
169 lines
4.8 KiB
C
/*
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* Copyright 2009 Extreme Engineering Solutions, Inc.
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* Copyright 2007-2008 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
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{
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i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
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sizeof(ddr2_spd_eeprom_t));
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}
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unsigned int fsl_ddr_get_mem_data_rate(void)
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{
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return get_bus_freq(0);
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}
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void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
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unsigned int ctrl_num)
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{
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unsigned int i;
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unsigned int i2c_address = 0;
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for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
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if (ctrl_num == 0) {
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i2c_address = SPD_EEPROM_ADDRESS1;
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#ifdef SPD_EEPROM_ADDRESS2
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} else if (ctrl_num == 1) {
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i2c_address = SPD_EEPROM_ADDRESS2;
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#endif
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} else {
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/* An inalid ctrl number was give, use default SPD */
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printf("ERROR: invalid DDR ctrl: %d\n", ctrl_num);
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i2c_address = SPD_EEPROM_ADDRESS1;
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}
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get_spd(&(ctrl_dimms_spd[i]), i2c_address);
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}
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}
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/*
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* There are four board-specific SDRAM timing parameters which must be
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* calculated based on the particular PCB artwork. These are:
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* 1.) CPO (Read Capture Delay)
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* - TIMING_CFG_2 register
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* Source: Calculation based on board trace lengths and
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* chip-specific internal delays.
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* 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
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* - TIMING_CFG_2 register
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* Source: Calculation based on board trace lengths.
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* Unless clock and DQ lanes are very different
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* lengths (>2"), this should be set to the nominal value
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* of 1/2 clock delay.
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* 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
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* - DDR_SDRAM_CLK_CNTL register
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* Source: Signal Integrity Simulations
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* 4.) 2T Timing on Addr/Ctl
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* - TIMING_CFG_2 register
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* Source: Signal Integrity Simulations
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* Usually only needed with heavy load/very high speed (>DDR2-800)
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*
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* PCB routing on the XPedite5170 is nearly identical to the XPedite5370
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* so we use the XPedite5370 settings as a basis for the XPedite5170.
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*/
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typedef struct board_memctl_options {
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uint16_t datarate_mhz_low;
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uint16_t datarate_mhz_high;
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uint8_t clk_adjust;
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uint8_t cpo_override;
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uint8_t write_data_delay;
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} board_memctl_options_t;
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static struct board_memctl_options bopts_ctrl[][2] = {
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{
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/* Controller 0 */
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{
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/* DDR2 600/667 */
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.datarate_mhz_low = 500,
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.datarate_mhz_high = 750,
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.clk_adjust = 5,
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.cpo_override = 8,
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.write_data_delay = 2,
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},
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{
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/* DDR2 800 */
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.datarate_mhz_low = 750,
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.datarate_mhz_high = 850,
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.clk_adjust = 5,
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.cpo_override = 9,
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.write_data_delay = 2,
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},
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},
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{
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/* Controller 1 */
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{
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/* DDR2 600/667 */
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.datarate_mhz_low = 500,
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.datarate_mhz_high = 750,
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.clk_adjust = 5,
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.cpo_override = 7,
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.write_data_delay = 2,
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},
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{
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/* DDR2 800 */
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.datarate_mhz_low = 750,
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.datarate_mhz_high = 850,
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.clk_adjust = 5,
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.cpo_override = 8,
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.write_data_delay = 2,
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},
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},
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
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sys_info_t sysinfo;
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int i;
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unsigned int datarate;
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get_sys_info(&sysinfo);
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datarate = fsl_ddr_get_mem_data_rate() / 1000000;
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for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
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if ((bopts[i].datarate_mhz_low <= datarate) &&
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(bopts[i].datarate_mhz_high >= datarate)) {
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debug("controller %d:\n", ctrl_num);
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debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
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debug(" cpo = %d\n", bopts[i].cpo_override);
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debug(" write_data_delay = %d\n",
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bopts[i].write_data_delay);
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popts->clk_adjust = bopts[i].clk_adjust;
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popts->cpo_override = bopts[i].cpo_override;
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popts->write_data_delay = bopts[i].write_data_delay;
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}
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}
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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}
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