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https://github.com/brain-hackers/u-boot-brain
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![Peter Tyser](/assets/img/avatar_default.png)
PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
187 lines
3.9 KiB
C
187 lines
3.9 KiB
C
/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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* Keith Outwater, keith_outwater@mvis.com.
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*
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* (C) Copyright 2008
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* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <ACEX1K.h>
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#include <command.h>
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#include "fpga.h"
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#include "mvblm7.h"
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#ifdef FPGA_DEBUG
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#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
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#else
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#define fpga_debug(fmt, args...)
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#endif
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Altera_CYC2_Passive_Serial_fns altera_fns = {
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fpga_null_fn,
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fpga_config_fn,
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fpga_status_fn,
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fpga_done_fn,
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fpga_wr_fn,
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fpga_null_fn,
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fpga_null_fn,
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};
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Altera_desc cyclone2 = {
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Altera_CYC2,
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passive_serial,
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Altera_EP2C20_SIZE,
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(void *) &altera_fns,
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NULL,
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0
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};
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DECLARE_GLOBAL_DATA_PTR;
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int mvblm7_init_fpga(void)
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{
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fpga_debug("Initialize FPGA interface\n");
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fpga_init();
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fpga_add(fpga_altera, &cyclone2);
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fpga_config_fn(0, 1, 0);
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udelay(60);
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return 1;
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}
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int fpga_null_fn(int cookie)
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{
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return 0;
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}
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int fpga_config_fn(int assert, int flush, int cookie)
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{
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
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u32 dvo = gpio->dat;
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fpga_debug("SET config : %s\n", assert ? "low" : "high");
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if (assert)
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dvo |= FPGA_CONFIG;
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else
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dvo &= ~FPGA_CONFIG;
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if (flush)
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gpio->dat = dvo;
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return assert;
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}
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int fpga_done_fn(int cookie)
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{
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
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int result = 0;
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udelay(10);
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fpga_debug("CONF_DONE check ... ");
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if (gpio->dat & FPGA_CONF_DONE) {
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fpga_debug("high\n");
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result = 1;
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} else
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fpga_debug("low\n");
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return result;
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}
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int fpga_status_fn(int cookie)
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{
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
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int result = 0;
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fpga_debug("STATUS check ... ");
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if (gpio->dat & FPGA_STATUS) {
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fpga_debug("high\n");
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result = 1;
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} else
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fpga_debug("low\n");
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return result;
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}
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int fpga_clk_fn(int assert_clk, int flush, int cookie)
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{
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
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u32 dvo = gpio->dat;
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fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
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if (assert_clk)
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dvo |= FPGA_CCLK;
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else
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dvo &= ~FPGA_CCLK;
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if (flush)
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gpio->dat = dvo;
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return assert_clk;
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}
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static inline int _write_fpga(u8 val, int dump)
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{
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
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int i;
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u32 dvo = gpio->dat;
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if (dump)
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fpga_debug(" %02x -> ", val);
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for (i = 0; i < 8; i++) {
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dvo &= ~FPGA_CCLK;
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gpio->dat = dvo;
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dvo &= ~FPGA_DIN;
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if (dump)
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fpga_debug("%d ", val&1);
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if (val & 1)
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dvo |= FPGA_DIN;
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gpio->dat = dvo;
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dvo |= FPGA_CCLK;
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gpio->dat = dvo;
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val >>= 1;
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}
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if (dump)
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fpga_debug("\n");
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return 0;
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}
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int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
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{
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unsigned char *data = (unsigned char *) buf;
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int i;
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fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
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for (i = 0; i < len; i++)
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_write_fpga(data[i], 0);
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fpga_debug("\n");
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return FPGA_SUCCESS;
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}
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